公开(公告)号：WO2007133356A1

公开(公告)日：2007-11-22

申请号：PCT/US2007/008798

申请日：2007-04-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  FANG, Sunfei ,  KNARR, Randolph, F. ,  KRISHNAN, Mahadevaiyer ,  LAVOIE, Christian ,  MO, Renee, T. ,  PRANATHARTHIHARAN, Balasubramanian ,  STRANE, Jay, W.

Inventor： FANG, Sunfei ,  KNARR, Randolph, F. ,  KRISHNAN, Mahadevaiyer ,  LAVOIE, Christian ,  MO, Renee, T. ,  PRANATHARTHIHARAN, Balasubramanian ,  STRANE, Jay, W.

IPC: H01L21/44 ,  C23F1/00

CPC classification number: H01L21/28518 ,  C23F1/28 ,  C23F1/30 ,  C23F1/44

Abstract: A method for forming self-aligned metal silicide contacts over at least two silicon-containing semiconductor regions that are spaced apart from each other by an exposed dielectric region is disclosed. Each of the self-aligned metal silicide contacts so formed comprises at least nickel silicide and platinum silicide with a substantially smooth surface, and the exposed dielectric region, is essentially free of metal and metal silicide. Nickel or nickel alloy deposition is followed by low-temperature annealing, nickel etching, high-temperature annealing, and aqua regla etching.

Abstract translation: 公开了一种用于在通过暴露的电介质区域彼此间隔开的至少两个含硅半导体区域上形成自对准金属硅化物接触的方法。 如此形成的每个自对准金属硅化物触点至少包括具有基本平滑表面的硅化镍和硅化铂，并且暴露的电介质区域基本上不含金属和金属硅化物。 镍或镍合金沉积之后是低温退火，镍蚀刻，高温退火和水蚀刻蚀刻。

公开(公告)号：WO2010123750A1

公开(公告)日：2010-10-28

申请号：PCT/US2010/031224

申请日：2010-04-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHANG, Josephine B. ,  CHANG, Leland ,  MO, Renee T. ,  NARAYANAN, Vijay ,  SLEIGHT, Jeffrey W.

Inventor： CHANG, Josephine B. ,  CHANG, Leland ,  MO, Renee T. ,  NARAYANAN, Vijay ,  SLEIGHT, Jeffrey W.

IPC: H01L21/335

CPC classification number: H01L29/7856 ,  H01L29/66795

Abstract: Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.

Abstract translation: 提供了多阈值电压（Vt）场效应晶体管（FET）器件及其制造技术。 一方面，提供一种FET器件，其包括源极区域; 漏区; 将源极和漏极区互连的至少一个沟道; 以及围绕通道的至少一部分的栅极，其被配置为由于在整个栅极中选择性地放置至少一个带边缘金属而具有多个阈值电压。

公开(公告)号：WO2008085686A3

公开(公告)日：2008-07-17

申请号：PCT/US2007/088266

申请日：2007-12-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  LIU, Yaochang ,  CHIDAMBARRAO, Dureseti ,  RIM, Kern ,  GLUSCHENKOV, Oleg ,  MO, Renee, T. ,  HOLT, Judson, R.

Inventor： LIU, Yaochang ,  CHIDAMBARRAO, Dureseti ,  RIM, Kern ,  GLUSCHENKOV, Oleg ,  MO, Renee, T. ,  HOLT, Judson, R.

IPC: H01L27/10 ,  H01L21/82

Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed suicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed suicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

公开(公告)号：WO2010114787A1

公开(公告)日：2010-10-07

申请号：PCT/US2010/029014

申请日：2010-03-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  BU, Huiming ,  CHUDZIK, Michael, P ,  HE, Wei ,  JHA, Rashmi ,  KIM, Young-hee ,  KRISHNAN, Siddarth, A. ,  MO, Renee, T. ,  MOUMEN, Naim ,  NATZLE, Wesley, C.

Inventor： BU, Huiming ,  CHUDZIK, Michael, P ,  HE, Wei ,  JHA, Rashmi ,  KIM, Young-hee ,  KRISHNAN, Siddarth, A. ,  MO, Renee, T. ,  MOUMEN, Naim ,  NATZLE, Wesley, C.

IPC: H01L21/336

CPC classification number: H01L21/28202 ,  H01L21/28176 ,  H01L21/28185 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.

Abstract translation: 形成器件的方法包括提供衬底，在衬底上形成界面层，在界面层上沉积高k电介质层，在高k电介质层上沉积氧气清除层并执行退火。 高k金属栅极晶体管包括衬底，衬底上的界面层，界面层上的高k电介质层和高k电介质层上的氧清除层。

公开(公告)号：WO2009120567A1

公开(公告)日：2009-10-01

申请号：PCT/US2009/037620

申请日：2009-03-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  NATZLE, Wesley ,  MO, Renee, T. ,  JHA, Rashmi ,  SCHONENBERG, Kathryn, T. ,  CONTI, Richard, A.

Inventor： NATZLE, Wesley ,  MO, Renee, T. ,  JHA, Rashmi ,  SCHONENBERG, Kathryn, T. ,  CONTI, Richard, A.

IPC: H01L21/4763

CPC classification number: H01L21/76224 ,  H01L21/28123 ,  H01L29/517

Abstract: A method of fabricating a semiconducting device that includes providing a substrate (5) having at least one semiconducting region (10) and at least one oxygen source region (20); forming an oxygen barrier material (25) atop portions of an upper surface of the at least one oxygen region (20); forming a high-k gate dielectric (31) on the substrate (5) including the at least one semiconducting region (10), wherein oxygen barrier material (25) separates the high-k gate dielectric (31) from the at least one oxygen source material (20); and forming a gate conductor (33) atop the high-k gate dielectric (31).

Abstract translation: 一种制造半导体器件的方法，其包括提供具有至少一个半导体区域（10）和至少一个氧源区域（20）的衬底（5）; 在所述至少一个氧区（20）的上表面的顶部的顶部上形成氧阻隔材料（25）; 在包括所述至少一个半导体区域（10）的衬底（5）上形成高k栅极电介质（31），其中氧阻挡材料（25）将所述高k栅极电介质（31）与所述至少一个氧气 源材料（20）; 以及在所述高k栅极电介质（31）的顶部形成栅极导体（33）。

公开(公告)号：WO2008106244A3

公开(公告)日：2010-03-18

申请号：PCT/US2008051067

申请日：2008-01-15

Applicant: IBM ,  CHUDZIK MICHAEL P ,  HE WEI ,  MO RENEE T ,  MOUMEN NAIM ,  NARAYANAN VIJAY ,  PARK DAE-GYU ,  PARUCHURI VAMSI K

Inventor： CHUDZIK MICHAEL P ,  HE WEI ,  MO RENEE T ,  MOUMEN NAIM ,  NARAYANAN VIJAY ,  PARK DAE-GYU ,  PARUCHURI VAMSI K

IPC: H01L21/335

CPC classification number: H01L21/823807 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78 ,  H01L29/7845

Abstract: A gate structure (200) for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack (116) having a first gate dielectric layer (102) formed over a substrate (100), and a first metal layer (106) formed over the first gate dielectric layer. A second gate stack (118) includes a second gate dielectric layer (102) formed over the substrate and a second metal layer (110) formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.

Abstract translation: 用于互补金属氧化物半导体（CMOS）器件的栅极结构（200）包括具有形成在衬底（100）上的第一栅极电介质层（102）的第一栅极堆叠（116）和形成在衬底 第一栅介质层。 第二栅极堆叠（118）包括形成在衬底上的第二栅极电介质层（102）和形成在第二栅极电介质层上的第二金属层（110）。 第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

公开(公告)号：WO2008106244A2

公开(公告)日：2008-09-04

申请号：PCT/US2008/051067

申请日：2008-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  CHUDZIK, Michael, P. ,  HE, Wei ,  MO, Renee, T. ,  MOUMEN, Naim ,  NARAYANAN, Vijay ,  PARK, Dae-Gyu ,  PARUCHURI, Vamsi, K.

Inventor： CHUDZIK, Michael, P. ,  HE, Wei ,  MO, Renee, T. ,  MOUMEN, Naim ,  NARAYANAN, Vijay ,  PARK, Dae-Gyu ,  PARUCHURI, Vamsi, K.

IPC: H01L21/8238 ,  H01L29/76

CPC classification number: H01L21/823807 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78 ,  H01L29/7845

Abstract: A gate structure (200) for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack (116) having a first gate dielectric layer (102) formed over a substrate (100), and a first metal layer (106) formed over the first gate dielectric layer. A second gate stack (118) includes a second gate dielectric layer (102) formed over the substrate and a second metal layer (110) formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.

Abstract translation: 用于互补金属氧化物半导体（CMOS）器件的栅极结构（200）包括具有形成在衬底（100）上的第一栅极电介质层（102）的第一栅极堆叠（116）和形成在衬底 第一栅介质层。 第二栅极堆叠（118）包括形成在衬底上的第二栅极电介质层（102）和形成在第二栅极电介质层上的第二金属层（110）。 第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

公开(公告)号：WO2008085686A2

公开(公告)日：2008-07-17

申请号：PCT/US2007088266

申请日：2007-12-20

Applicant: IBM ,  LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

Inventor： LIU YAOCHANG ,  CHIDAMBARRAO DURESETI ,  RIM KERN ,  GLUSCHENKOV OLEG ,  MO RENEE T ,  HOLT JUDSON R

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed suicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed suicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

Abstract translation: 虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。 本发明提供了在放置在半导体衬底上的硅合金表面上提供非合金硅化物的结构和方法。 这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。 此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。