公开(公告)号：WO2007115120A2

公开(公告)日：2007-10-11

申请号：PCT/US2007/065539

申请日：2007-03-29

Applicant: ATMEL CORPORATION ,  WANG, Liqi ,  SON, Jinshu ,  NG, Philip ,  CHAN, Johnny

Inventor： WANG, Liqi ,  SON, Jinshu ,  NG, Philip ,  CHAN, Johnny

IPC: A23J1/02

CPC classification number: G01R31/40 ,  G01R31/3004

Abstract: Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of the integrated circuit is coupled to the output of the driver circuit. The driver circuit may be enabled by a signal provided on a third I/O pad of the integrated circuit.

Abstract translation: 用于测试集成电路中的上电复位电路的电路包括耦合到集成电路的第一I / O焊盘的高电压检测器。 集成电路中的上电复位电路具有耦合到由高电压供电的驱动器电路的输出。 集成电路的第二I / O焊盘耦合到驱动器电路的输出端。 可以通过集成电路的第三I / O焊盘上提供的信号使能驱动器电路。

公开(公告)号：WO2007018985A2

公开(公告)日：2007-02-15

申请号：PCT/US2006/027914

申请日：2006-07-18

Applicant: ATMEL CORPORATION ,  CHAN, Johnny ,  SON, Jinshu ,  NG, Philip, S.

Inventor： CHAN, Johnny ,  SON, Jinshu ,  NG, Philip, S.

IPC: G11C16/04 ,  G11C16/06 ,  G11C11/34

CPC classification number: G11C16/28

Abstract: An array (200; 202) of memory cells having a predetermined group (301) of storage cells (203; 205; 306) , arranged in a row, also have an arrangement of one or more reference cells (201; 207; 304, 307) fabricated to be adjacent to or proximate to the row of storage cells. The reference cells are written to, erased, or programmed when the storage cells are written to, erased, or programmed. The same number of write, erase, or program cycles and the proximity of the reference cells to the storage cells maintain an operational matching of the storage cells and reference cells.

Abstract translation: 具有排列成行的预定组（301）存储单元（203; 205; 306）的存储器单元的阵列（200; 202）也具有一个或多个参考 制造成与该行存储单元相邻或邻近的单元（201; 207; 304,307）。 当存储单元被写入，擦除或编程时，参考单元被写入，擦除或编程。 相同数量的写入，擦除或编程周期以及参考单元与存储单元的接近度保持存储单元和参考单元的操作匹配。

公开(公告)号：WO2006110239A1

公开(公告)日：2006-10-19

申请号：PCT/US2006/008448

申请日：2006-03-08

Applicant: ATMEL CORPORATION ,  SON, Jinshu ,  WANG, Liqi ,  LE, Minh, V. ,  NG, Philip, S.

Inventor： SON, Jinshu ,  WANG, Liqi ,  LE, Minh, V. ,  NG, Philip, S.

IPC: G11C7/10

CPC classification number: G11C8/10 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1048

Abstract: A multiplexer circuit in a memory organized into page-portions (210, 250) has a plurality of bit- select multiplexers (216, 256) configured to couple a plurality of page-portion global bitlines (214, 254) to a sense amplifier (201) input. A plurality of column address lines organized into data bytes comprises each page-portion. A plurality of column multiplexers (212, 252) couple the data bytes to the page-portion global bitlines (214, 254) such that each of the address lines comprising the data byte is coupled to one of the page-portion global bitlines (214, 254).

Abstract translation: 被组织成页面部分（210,250）的存储器中的多路复用器电路具有多个位选择多路复用器（216,256），其被配置为将多个页面部分全局位线（214,254）耦合到读出放大器 201）输入。 组织成数据字节的多个列地址线包括每个页面部分。 多个列复用器（212,252）将数据字节耦合到页面部分全局位线（214,254），使得包括数据字节的每个地址线被耦合到页面部分全局位线之一（214 ，254）。

公开(公告)号：WO2007115120A3

公开(公告)日：2008-11-06

申请号：PCT/US2007065539

申请日：2007-03-29

Applicant: ATMEL CORP ,  WANG LIQI ,  SON JINSHU ,  NG PHILIP ,  CHAN JOHNNY

Inventor： WANG LIQI ,  SON JINSHU ,  NG PHILIP ,  CHAN JOHNNY

IPC: G01R31/28

CPC classification number: G01R31/40 ,  G01R31/3004

Abstract: Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of the integrated circuit is coupled to the output of the driver circuit. The driver circuit may be enabled by a signal provided on a third I/O pad of the integrated circuit.

Abstract translation: 用于测试集成电路中的上电复位电路的电路包括耦合到集成电路的第一I / O焊盘的高电压检测器。 集成电路中的上电复位电路具有耦合到由高电压供电的驱动器电路的输出。 集成电路的第二I / O焊盘耦合到驱动器电路的输出端。 可以通过集成电路的第三I / O焊盘上提供的信号使能驱动器电路。

公开(公告)号：WO2007118050A2

公开(公告)日：2007-10-18

申请号：PCT/US2007/065782

申请日：2007-04-02

Applicant: ATMEL CORPORATION ,  CHAN, Johnny ,  NG, Philip

Inventor： CHAN, Johnny ,  NG, Philip

IPC: H03K5/22

CPC classification number: H03K5/24

Abstract: A method for sensing voltage on an internal node in an integrated circuit includes applying a voltage larger than a threshold value to a first pad, generating from the activation voltage a potential for a sensing circuit and coupled to the internal node, and coupling an output of the sensing circuit to a second pad on the integrated circuit when the activation voltage is present on the first pad. A sensing circuit includes first and second pads, a voltage-sensor circuit having an input coupled to an internal node and a power connection coupled to a sensor power node. A circuit is configured to place a supply potential on the sensor power node when a threshold value is on the first pad. A switch coupled between the sensing circuit and the second pad turns on when the supply potential is on the voltage sensor power node.

Abstract translation: 用于感测集成电路中的内部节点上的电压的方法包括将大于阈值的电压施加到第一焊盘，从激活电压产生感测电路的电位并耦合到内部节点，并将 当激活电压存在于第一焊盘上时，感测电路连接到集成电路上的第二焊盘。 感测电路包括第一和第二焊盘，具有耦合到内部节点的输入的电压传感器电路和耦合到传感器功率节点的电力连接。 电路被配置为当阈值位于第一焊盘上时，在传感器电源节点上放置电源。 当电源位于电压传感器功率节点上时，耦合在感测电路和第二焊盘之间的开关导通。

公开(公告)号：WO0052187A2

公开(公告)日：2000-09-08

申请号：PCT/US0005844

申请日：2000-03-03

Applicant: MERCK & CO INC ,  GRAHAM FRANK L ,  PARKS ROBIN ,  NG PHILIP

Inventor： GRAHAM FRANK L ,  PARKS ROBIN ,  NG PHILIP

IPC: C12N15/09 ,  A61K35/76 ,  A61K48/00 ,  C12N5/10 ,  C12N7/00 ,  C12N15/861 ,  C12N9/00 ,  C12N15/90

CPC classification number: C12N7/00 ,  C12N15/86 ,  C12N2710/10343 ,  C12N2710/10351 ,  C12N2800/30

Abstract: In the present invention, viruses, plasmids or both are constructed which contain viral DNA, either at least one head-to-head ITR junction, recombinase recognition sites positioned such that site-specific recombination between recombinase recognition sites in separate plasmids results in generation of infectious viral DNA at high-efficiency in cotransfected host cells that have been engineered to express a site-specific recombinase, or both. Because of the high-efficiency and specificity of the Cre enzyme, the FLP enzyme, or both, suitably engineered plasmids can be readily recombined to produce infectious virus at high-efficiency in cotransfected 293 cells, without, at the same time, producing wild-type adenovirus, with the attendant problems for removal thereof. Use of recombinases besides Cre or FLP, and recombinase recognition sites besides lox or frt sites, and use of cells other than 293 cells are also disclosed and enabled, as are kits incorporating the site-specific vector system, as well as compositions and methods for using such compositions as vaccines or in gene therapeutic applications. Enhancements in the efficiency of both site-specific and homologous recombination are provided by inclusion of at least one head-to-head ITR junction.

Abstract translation: 在本发明中，构建了包含病毒DNA的病毒，质粒或两者，至少一个头对头ITR接头，重组酶识别位点，使得分离质粒中重组酶识别位点之间的位点特异性重组导致产生 共转染的宿主细胞中高效率的感染性病毒DNA已被工程化以表达位点特异性重组酶，或两者兼有。 由于Cre酶的高效率和特异性，FLP酶或两者合适工程改造的质粒可以在共转染的293细胞中以高效率容易地重组以产生感染性病毒，而不同时产生野生型， 型腺病毒，伴随其去除的问题。 除了使用Cre或FLP之外的重组酶以及除了lox或frt位点之外的重组酶识别位点以及除293细胞以外的细胞的使用也被公开和使能，以及包含位点特异性载体系统的试剂盒以及组合物和方法 使用这样的组合物作为疫苗或在基因治疗应用中。 通过包含至少一个头对头ITR连接来提供位点特异性和同源重组的效率的增强。

公开(公告)号：WO2007065108A3

公开(公告)日：2009-01-15

申请号：PCT/US2006061349

申请日：2006-11-29

Applicant: ATMEL CORP ,  NG PHILIP S ,  SON JINSHU ,  CHAN JOHNNY

Inventor： NG PHILIP S ,  SON JINSHU ,  CHAN JOHNNY

IPC: G05F1/10

CPC classification number: G11C5/145 ,  G11C5/147

Abstract: A high-voltage charge pump circuit includes a charge pump circuit. First high-voltage output circuit is configured to set an output voltage of the charge pump at a first voltage level selected for regular programming and erasing memory cells. A second high-voltage output circuit is configured to set the output voltage of the charge pump at a second voltage level selected for walkout of device junctions, the second voltage level being higher than the first voltage level. A third high-voltage output circuit is configured to set the output voltage of the charge pump at a third voltage level selected for guardband programming and erasing, the third voltage level being lower than the second voltage level and higher than the first voltage level. Selection circuitry selectively couples one of the first, second, and third high- voltage output circuits to the output of the high-voltage charge pump circuit.

Abstract translation: 高压电荷泵电路包括电荷泵电路。 第一高电压输出电路被配置为将电荷泵的输出电压设置在为正常编程和擦除存储器单元所选择的第一电压电平。 第二高电压输出电路被配置为将电荷泵的输出电压设置为选择用于器件结的去除的第二电压电平，第二电压电平高于第一电压电平。 第三高压输出电路被配置为将电荷泵的输出电压设置为选择用于保护带编程和擦除的第三电压电平，第三电压电平低于第二电压电平并高于第一电压电平。 选择电路将第一，第二和第三高压输出电路中的一个选择性地耦合到高压电荷泵电路的输出。

公开(公告)号：WO2008150420A1

公开(公告)日：2008-12-11

申请号：PCT/US2008/006795

申请日：2008-05-29

Applicant: ATMEL CORPORATION ,  NG, Philip, S. ,  YE, Ken

Inventor： NG, Philip, S. ,  YE, Ken

IPC: G08B23/00

CPC classification number: H04L12/40045 ,  H04L12/40032 ,  H04L2012/40273

Abstract: Embodiments disclosed are apparatus comprising a processing circuit having signal and power input ports to couple to a single-wire interface providing electncal communication of both signals and power at a power supply voltage level Also provided Is a charging transistor coupled at a first source/dram terminal to the single-wire interface Further provided is a charge storage device coupled to the second source/drain terminal of the transistor at a connection point and to the power input port of the processing circuit at said connection point There is also a control device having an input coupled to the single-wire interface, a control output coupled to the gate of the transistor, and powered by the charge storage device at the connection point, such that the transistor charges the storage device when the single-wire interface voltage is at a power supply voltage level.

Abstract translation: 所公开的实施例包括具有信号和功率输入端口以耦合到单线接口的处理电路的装置，该单线接口提供电源电压电平上的两个信号和功率的电气通信。还提供了一个连接在第一源极/ 还提供了一种电荷存储装置，其在连接点处连接到晶体管的第二源极/漏极端子，并且在所述连接点处连接到处理电路的电力输入端口。还有一种控制装置，其具有 耦合到单线接口的输入，耦合到晶体管的栅极的控制输出，并且由连接点处的电荷存储装置供电，使得当单线接口电压处于 电源电压电平。

公开(公告)号：WO2012082864A1

公开(公告)日：2012-06-21

申请号：PCT/US2011/064854

申请日：2011-12-14

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC ,  KEGEL, Andy ,  HUMMEL, Mark ,  GLASER, Steve ,  ASARO, Anthony ,  NG, Philip ,  CHENG, Jeffrey

Inventor： KEGEL, Andy ,  HUMMEL, Mark ,  GLASER, Steve ,  ASARO, Anthony ,  NG, Philip ,  CHENG, Jeffrey

IPC: G06F12/10

CPC classification number: G06F12/109 ,  G06F12/1009 ,  G06F12/1081 ,  G06F2212/151

Abstract: Embodiments of the present invention provide methods, systems, and computer readable media for input output memory management unit (IOMMU) two-layer addressing in the context of memory address translations for I/O devices. According to an embodiment, a method includes translating a guest virtual address (GVA) to a corresponding guest physical address (GPA) using a guest address translation table according to a process address space identifier associated with an address translation transaction associated with an I/O device, and translating the GPA to a corresponding system physical address (SPA) using a system address translation table according to a device identifier associated with the address translation transaction.

Abstract translation: 本发明的实施例提供了用于I / O设备的存储器地址转换的上下文中的输入输出存储器管理单元（IOMMU）双层寻址的方法，系统和计算机可读介质。 根据实施例，一种方法包括根据与与I / O相关联的地址转换事务相关联的进程地址空间标识符，使用访客地址转换表将访客虚拟地址（GVA）翻译成相应的客体物理地址（GPA） 设备，并且根据与地址转换事务相关联的设备标识符，使用系统地址转换表将GPA转换为相应的系统物理地址（SPA）。

公开(公告)号：WO2007124304A3

公开(公告)日：2008-04-17

申请号：PCT/US2007066779

申请日：2007-04-17

Applicant: ATMEL CORP ,  NG PHILIP S ,  SON JINSHU

Inventor： NG PHILIP S ,  SON JINSHU

IPC: G06F13/00

CPC classification number: H03K19/01721 ,  H03K19/01742

Abstract: A dual-wire communications bus circuit (300), compatible with existing two-wire bus protocols, includes a first and second part of the communications bus circuit to couple to a communications bus (317) The bus has a first line for carrying data signals from a master device (201 ) to one or more slave devices (315A-315H) and a second line to carry a clock signal between the devices A pullup resistor (305, 311 ) is located in each part of the communications bus circuit, the pullup resistor (305) in the first part couples to the first line of the communications bus (317) and the pullup resistor (311) in the second part couples to the second line of the communications bus (317) To improve data throughput and reduce noise, an active pullup device (301A2-301 H2), working in conjunction with the pullup resistor (311 ), is located in each part of the communications bus circuit

Abstract translation: 与现有的双线总线协议兼容的双线通信总线电路（300）包括通信总线电路的第一和第二部分以耦合到通信总线（317）。总线具有用于承载数据信号的第一线 从主设备（201）到一个或多个从设备（315A-315H）和第二线路，以在设备之间携带时钟信号。上拉电阻器（305,311）位于通信总线电路的每个部分中， 第一部分中的上拉电阻（305）耦合到通信总线（317）的第一行，并且第二部分中的上拉电阻（311）耦合到通信总线（317）的第二行。为了提高数据吞吐量并减少 噪声，与上拉电阻（311）一起工作的有源上拉装置（301A2-301 H2）位于通信总线电路的每个部分