CIS REACTIVE OXYGEN QUENCHERS INTEGRATED INTO LINKERS
    5.
    发明申请
    CIS REACTIVE OXYGEN QUENCHERS INTEGRATED INTO LINKERS 审中-公开
    CIS反应性氧气检测器集成到连接器中

    公开(公告)号:WO2009100382A1

    公开(公告)日:2009-08-13

    申请号:PCT/US2009/033467

    申请日:2009-02-06

    CPC classification number: C12Q1/48 C07H21/00 C12Q1/68 C12Q1/686

    Abstract: The present invention provides methods and compositions for performing illuminated reactions, particularly sequencing reactions, while mitigating and/or preventing photodamage to reactants that can result from prolonged illumination. In particular, the invention provides methods and compositions for incorporating photoprotective agents into conjugates comprising reporter molecules and nucleoside polyphosphates.

    Abstract translation: 本发明提供用于进行照明反应,特别是测序反应的方法和组合物,同时减轻和/或防止可能由长时间照射引起的反应物的光损伤。 特别地,本发明提供了将光保护剂掺入包含报道分子和核苷多磷酸盐的缀合物中的方法和组合物。

    MULTIPLE-CORE PROCESSOR WITH HIERARCHICAL MICROCODE STORE
    6.
    发明申请
    MULTIPLE-CORE PROCESSOR WITH HIERARCHICAL MICROCODE STORE 审中-公开
    具有分层微处理器的多核处理器

    公开(公告)号:WO2009011913A1

    公开(公告)日:2009-01-22

    申请号:PCT/US2008/008802

    申请日:2008-07-18

    CPC classification number: G06F9/28 G06F9/223

    Abstract: A multiple-core processor having a hierarchical microcode store. A processor may include multiple processor cores, each configured to independently execute instructions defined according to a programmer-visible instruction set architecture (ISA). Each core may include a respective local microcode unit configured to store microcode entries. The processor may also include a remote microcode unit accessible by each of the processor cores. Any given one of the processor cores may be configured to generate a given microcode entrypoint corresponding to a particular microcode entry including one or more operations to be executed by the given processor core, and to determine whether the particular microcode entry is stored within the respective local microcode unit of the given core. In response to determining that the particular microcode entry is not stored within the respective local microcode unit, the given core may convey a request for the particular microcode entry to the remote microcode unit.

    Abstract translation: 具有分级微代码存储器的多核处理器。 处理器可以包括多个处理器核心,每个处理器核心被配置为独立地执行根据编程器 - 可见指令集架构(ISA)定义的指令。 每个核心可以包括被配置为存储微代码条目的相应的本地微代码单元。 处理器还可以包括可由每个处理器核心访问的远程微代码单元。 任何给定的一个处理器核心可以被配置为生成对应于特定微代码条目的给定微代码入口点,该特定微代码条目包括要由给定处理器核心执行的一个或多个操作,并且确定特定微代码条目是否存储在相应的本地 给定核心的微码单元。 响应于确定特定微代码条目不存储在相应的本地微代码单元内,给定的核心可以向远程微代码单元传达特定微代码条目的请求。

    CONTROLLED INITIATION OF PRIMER EXTENSION
    7.
    发明申请
    CONTROLLED INITIATION OF PRIMER EXTENSION 审中-公开
    控制引擎扩展

    公开(公告)号:WO2007147110A3

    公开(公告)日:2008-11-27

    申请号:PCT/US2007071327

    申请日:2007-06-15

    CPC classification number: C12Q1/6874 C12Q2561/113 C12Q2525/186 C12Q2523/313

    Abstract: Controlled initiation of primer extension in determination of nucleic acid sequence information by incorporation of nucleotides or nucleotide analogs. Preferred aspects include photo-initiated extension through the use of photo-cleavable blocking groups on termini of primer sequences followed by non-terminating primer extension using nucleotides or nucleotide analogs that are not extension terminators.

    Abstract translation: 通过掺入核苷酸或核苷酸类似物来测定核酸序列信息中引物延伸的控制引发。 优选的方面包括通过在引物序列的末端使用可光切割的封闭基团,然后使用不是延伸终止子的核苷酸或核苷酸类似物进行非终止引物延伸的光引发延伸。

    PROCESSING PIPELINE HAVING STAGE-SPECIFIC THREAD SELECTION AND METHOD THEREOF
    8.
    发明申请
    PROCESSING PIPELINE HAVING STAGE-SPECIFIC THREAD SELECTION AND METHOD THEREOF 审中-公开
    具有特殊螺纹选择的加工管道及其方法

    公开(公告)号:WO2009085086A1

    公开(公告)日:2009-07-09

    申请号:PCT/US2008/013302

    申请日:2008-12-03

    CPC classification number: G06F9/3867 G06F9/3851 G06F9/3891

    Abstract: One or more processor cores (102, 104, 106, 108) of a multiple-core processing device (100) each can utilize a processing pipeline (800) having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fetch, decode and dispatch resources. Further, one or more of the processor cores (102, 104, 106, 108) each can implement dispatch resources configured to dispatch multiple instructions in parallel to multiple corresponding execution units via separate dispatch buses. The dispatch resources further can opportunistically decode and dispatch instruction operations from multiple threads in parallel so as to increase the dispatch bandwidth. Moreover, some or all of the stages (802, 804, 806) of the processing pipelines (800) of one or more of the processor cores (102, 104, 106, 108) can be configured to implement independent thread selection for the corresponding stage.

    Abstract translation: 多核处理设备(100)的一个或多个处理器核心(102,104,106,108)各自可以利用具有多个执行单元(例如,整数执行单元或浮点单元)的处理流水线(800) 一起共享具有指令获取,解码和调度资源的预执行前端。 此外,一个或多个处理器核心(102,104,106,108)可以实现调度资源,配置为通过分开的调度总线并行分配多个相应执行单元的多个指令。 调度资源还可以并行地从多个线程机会地解码和分派指令操作,以增加调度带宽。 而且,一个或多个处理器核心(102,104,106,108)中的一个或多个处理器核心(102,104,106,108)的处理流水线(800)的一些或全部阶段(802,804,806)可以被配置为实现对应的 阶段。

    METHOD AND APPARATUS FOR LENGTH DECODING AND IDENTIFYING BOUNDARIES OF VARIABLE LENGTH INSTRUCTIONS
    9.
    发明申请
    METHOD AND APPARATUS FOR LENGTH DECODING AND IDENTIFYING BOUNDARIES OF VARIABLE LENGTH INSTRUCTIONS 审中-公开
    用于长度解码和识别可变长度指令边界的方法和装置

    公开(公告)号:WO2009009093A1

    公开(公告)日:2009-01-15

    申请号:PCT/US2008/008466

    申请日:2008-07-10

    CPC classification number: G06F9/3822 G06F9/30152 G06F9/3814 G06F9/382

    Abstract: A mechanism for superscalar decode of variable length instructions. A length decode unit may obtain a plurality of instruction bytes based on a scan window of a predetermined size. The instruction bytes may be associated with a plurality of variable length instructions, which are scheduled to be executed by a processing unit. The length decode unit may, for each instruction byte, estimate the start of a next variable length instruction following a current variable length instruction, and store a first pointer. A pre- pick unit may, for each instruction byte, use the first pointer to estimate the start of a subsequent variable length instruction following the next variable length instruction within the scan window, and store a second pointer. A pick unit may use a start pointer and related first and second pointers to determine the actual start of the variable length instructions within the scan window, and generate instruction pointers.

    Abstract translation: 用于可变长度指令的超标量解码的机制。 长度解码单元可以基于预定大小的扫描窗口获得多个指令字节。 指令字节可以与被调度为由处理单元执行的多个可变长度指令相关联。 对于每个指令字节,长度解码单元可以估计当前可变长度指令之后的下一可变长度指令的开始,并存储第一指针。 对于每个指令字节,预选单元可以使用第一指针来估计在扫描窗口内的下一可变长度指令之后的后续可变长度指令的开始,并存储第二指针。 拾取单元可以使用起始指针和相关的第一和第二指针来确定扫描窗口内的可变长度指令的实际开始,并且生成指令指针。

    CONTROLLED INITIATION OF PRIMER EXTENSION
    10.
    发明申请
    CONTROLLED INITIATION OF PRIMER EXTENSION 审中-公开
    控制引擎扩展

    公开(公告)号:WO2007147110A2

    公开(公告)日:2007-12-21

    申请号:PCT/US2007/071327

    申请日:2007-06-15

    CPC classification number: C12Q1/6874 C12Q2561/113 C12Q2525/186 C12Q2523/313

    Abstract: Controlled initiation of primer extension in determination of nucleic acid sequence information by incorporation of nucleotides or nucleotide analogs. Preferred aspects include photo-initiated extension through the use of photo-cleavable blocking groups on termini of primer sequences followed by non-terminating primer extension using nucleotides or nucleotide analogs that are not extension terminators.

    Abstract translation: 通过掺入核苷酸或核苷酸类似物来测定核酸序列信息中引物延伸的控制引发。 优选的方面包括通过在引物序列的末端使用可光切割的封闭基团,然后使用不是延伸终止子的核苷酸或核苷酸类似物进行非终止引物延伸的光引发延伸。

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