THIN FILM TRANSISTOR ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE
    1.
    发明申请
    THIN FILM TRANSISTOR ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE 审中-公开
    薄膜晶体管阵列基板及其制造方法及显示装置

    公开(公告)号:WO2017045135A1

    公开(公告)日:2017-03-23

    申请号:PCT/CN2015/089658

    申请日:2015-09-15

    Abstract: A method for forming a thin film transistor array substrate (110) comprises forming an active layer (140) using a zinc target under an environment of oxygen and nitrogen in a sputtering chamber, and forming a source/drain buffer layer (151/152) on the active layer (140) using the zinc target by a sputtering process in the sputtering chamber under an environment containing one of oxygen and nitrogen. A thin film transistor array substrate (110) comprises an active layer (140), a source/drain buffer layer (151/152) on and in contact with the active layer (140), wherein the active layer (140) is made of oxynitride compound of zinc, and the source/drain buffer layer (151/152) is made of one of an oxide and a nitride of zinc. A display device comprising the thin film transistor array substrate (110) is also provided.

    Abstract translation: 一种形成薄膜晶体管阵列基板(110)的方法包括:在溅射室内,在氧和氮环境下使用锌靶形成有源层(140),形成源/漏缓冲层(151/152) 在包含氧和氮的环境的环境中,通过溅射工艺在溅射室中使用锌靶在有源层(140)上。 薄膜晶体管阵列基板(110)包括有源层(140),与有源层(140)接触并与其接触的源极/漏极缓冲层(151/152),其中有源层(140)由 锌的氮氧化物化合物和源极/漏极缓冲层(151/152)由锌的氧化物和氮化物之一构成。 还提供了包括薄膜晶体管阵列基板(110)的显示装置。

    ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE

    公开(公告)号:WO2019028670A1

    公开(公告)日:2019-02-14

    申请号:PCT/CN2017/096409

    申请日:2017-08-08

    Inventor: XIE, Dini LI, Wei

    CPC classification number: G02F1/136 G02F2001/13606 G02F2202/22

    Abstract: An array substrate has a plurality of thin film transistors (100), a display apparatus, and a method of fabricating an array substrate. The array substrate includes a base substrate (10); a semiconductor layer (400) on the base substrate (10) and including a plurality of active layers (40) respectively for the plurality of thin film transistors (100); and an electrostatic discharging layer (300) electrically connected to the semiconductor layer (400) and configured to discharge electrostatic charge in the semiconductor layer (400).

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