公开(公告)号：WO2004061903A3

公开(公告)日：2005-04-14

申请号：PCT/US0339878

申请日：2003-12-16

Applicant: EASIC CORP

Inventor： OR-BACH ZVI ,  COOKE LAURENCE ,  APOSTOL ADRIAN ,  IACOBUT ROMEO

IPC: H01L20060101 ,  H01L21/44 ,  H01L21/60 ,  H01L23/31 ,  H01L23/34 ,  H01L23/485 ,  H01L27/10 ,  H01L27/118

CPC classification number: H01L28/20 ,  H01L23/3114 ,  H01L24/10 ,  H01L27/11803 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05005 ,  H01L2224/05541 ,  H01L2924/00014

Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os (36) and also including the step of forming redistribution layer (32) for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

Abstract translation: 提出了一种新颖的方法来为ASIC提供大幅降低的NRE和体积灵活性。 本发明包括一种制造集成电路的方法，包括以下步骤：提供半导体衬底，形成包括多个区域I / O（36）的无边界逻辑阵列，还包括形成再分配层（32）的步骤，用于 为了设备包装的目的，至少部分区域I / O重新分配。 该制造可以利用直接写电子束进行定制。 定制步骤可以包括制造与同一晶片不同体积的各种类型的装置。