公开(公告)号：WO2012009520A2

公开(公告)日：2012-01-19

申请号：PCT/US2011043987

申请日：2011-07-14

Applicant: QUALCOMM INC ,  CHANDRASEKARAN ARVIND ,  GU SHIQUN ,  HAU-RIEGE CHRISTINE S

Inventor： CHANDRASEKARAN ARVIND ,  GU SHIQUN ,  HAU-RIEGE CHRISTINE S

IPC: H01L21/60

CPC classification number: H01L24/81 ,  H01L21/76877 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/051 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/1161 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/3841 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Electromigration in microbump connections causes voids in the microbumps, which reduces the lifetime of an integrated circuit containing the microbump. Electromigration lifetime may be increased in microbumps by forming a copper shell around the solder. The copper shell of one microbump contacts the copper shell of a second microbump to enclose the solder of the microbump connection. The copper shell allows higher current densities through the microbump. Thus, smaller microbumps may be manufactured on a smaller pitch without suffering failure from electromigration. Additionally, the copper shell reduces shorting or bridging between microbump connections on a substrate.

Abstract translation: 微型接头中的电迁移会导致微胶囊中的空隙，从而降低了包含微型电池的集成电路的使用寿命。 通过在焊料周围形成铜壳，可能会在微胶囊中增加电迁移寿命。 一个微型块的铜壳接触第二个微型块的铜壳，以封闭微型接头的焊料。 铜壳允许通过微型块的更高的电流密度。 因此，可以以更小的间距制造较小的微胶片，而不会发生电迁移的故障。 此外，铜壳减少了衬底上的微型接头之间的短路或桥接。

公开(公告)号：WO2008001283A3

公开(公告)日：2008-05-29

申请号：PCT/IB2007052390

申请日：2007-06-20

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  SUDOL WOJTEK ,  WILSON MARTHA

Inventor： SUDOL WOJTEK ,  WILSON MARTHA

IPC: H01L23/485 ,  H01L21/60 ,  H01L21/607

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/16013 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16148 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2924/0001 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00014 ,  H01L2224/83851

Abstract: A flip-chip electrical coupling between first and second electrical components (250, 260). The coupling includes a bump (210) and a pad (220). The bump (210) is electrically coupled to the first electrical component (250). The pad (220) is electrically coupled to the second electrical component (260). The pad (220) is electrically coupled to and dimensioned smaller than a corresponding coupling surface (214) of the bump (210). The pad (220) and bump (210) may be electrically coupled together using an ultrasonic stub bump bonding process, conductive epoxy, etc.

Abstract translation: 第一和第二电部件（250,260）之间的倒装芯片电耦合。 该连接件包括凸块（210）和垫（220）。 凸块（210）电耦合到第一电气部件（250）。 垫（220）电耦合到第二电气部件（260）。 垫（220）电耦合到并且尺寸小于凸块（210）的对应耦合表面（214）。 垫（220）和凸块（210）可以使用超声波短截凸块接合工艺，导电环氧树脂等电耦合在一起

公开(公告)号：WO2007024587A2

公开(公告)日：2007-03-01

申请号：PCT/US2006/031933

申请日：2006-08-16

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  COYLE, Anthony, L. ,  LANGE, Bernhard, P.

Inventor： COYLE, Anthony, L. ,  LANGE, Bernhard, P.

IPC: H01L29/00

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/4334 ,  H01L23/4951 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A high current semiconductor device (for example QFN for 30 to 70 A) with low resistance and low inductance is encapsulated by molding compound (401, height 402 about 0.9 mm) so that the second lead surfaces (110b) remain un-encapsulated. A copper heat slug (404) may be attached to chip surface (101b) using thermally conductive adhesive (403). Chip surface (101a), protected by an overcoat (103) has metallization traces (102). Copper-filled windows contact the traces and copper layers (105) parallel to traces. Copper bumps (108) are formed on each line in an orderly and repetitive arrangement so that the bumps of one line are positioned about midway between the bumps of the neighboring lines. A substrate has elongated leads (110) oriented at right angles to the lines; the leads connect the corresponding bumps of alternating lines.

Abstract translation: 具有低电阻和低电感的高电流半导体器件（例如30至70A的QFN）通过模制化合物（401，高度402约0.9mm）封装，使得第二引线表面（110b）保持未封装。 铜散热片（404）可以使用导热粘合剂（403）附接到切屑表面（101b）。 由外涂层（103）保护的芯片表面（101a）具有金属化迹线（102）。 铜填充窗口与走线平行的迹线和铜层（105）接触。 在每条线上以有序且重复的布置形成铜凸块（108），使得一条线的凸起位于相邻线的凸块之间的中间。 衬底具有与线成直角定向的细长引线（110） 引线连接相应的交替线路凸起。

公开(公告)号：WO2006052763A2

公开(公告)日：2006-05-18

申请号：PCT/US2005040049

申请日：2005-11-04

Applicant: MICROCHIPS INC ,  COPPETA JONATHAN R ,  SHELTON KURT ,  SHEPPARD NORMAN F JR ,  SNELL DOUGLAS B

Inventor： COPPETA JONATHAN R ,  SHELTON KURT ,  SHEPPARD NORMAN F JR ,  SNELL DOUGLAS B

IPC: B81B7/00 ,  A61K9/00 ,  A61K9/20 ,  B23K20/02

CPC classification number: B81C1/00269 ,  A61K9/0097 ,  A61M5/14276 ,  A61M2205/0244 ,  A61M2207/00 ,  B23K20/02 ,  B33Y80/00 ,  B81B2201/06 ,  B81C1/00047 ,  B81C1/00095 ,  B81C2203/0109 ,  B81C2203/019 ,  B81C2203/038 ,  F16B4/004 ,  F16B5/08 ,  F16B11/004 ,  H01L23/10 ,  H01L23/3142 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/16237 ,  H01L2224/81193 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1461 ,  Y10T403/477 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Compression cold welding methods, joint structures, and hermetically sealed containment devices are provided. The method includes providing a first substrate having at least one first joint structure which comprises a first joining surface, which surface comprises a first metal; providing a second substrate having at least one second joint structure which comprises a second joining surface, which surface comprises a second metal; and compressing together the at least one first joint structure and the at least one second joint structure to locally deform and shear the joining surfaces at one or more interfaces in an amount effective to form a metal-to-metal bond between the first metal and second metal of the joining surfaces. Overlaps at the joining surfaces are effective to displace surface contaminants and facilitate intimate contact between the joining surfaces without heat input. Hermetically sealed devices can contain drug formulations, biosensors, or MEMS devices.

Abstract translation: 提供了压缩冷焊方法，接头结构和密封的密封装置。 该方法包括提供具有至少一个第一接合结构的第一基板，该第一接合结构包括第一接合表面，该表面包括第一金属; 提供具有至少一个第二接合结构的第二基板，所述第二接合结构包括第二接合表面，所述表面包括第二金属; 以及将所述至少一个第一接头结构和所述至少一个第二接头结构压缩在一起以在一个或多个界面处局部地变形和剪切所述接合表面，其量有效地形成所述第一金属与所述第二金属之间的金属 - 金属结合 接合表面的金属。 在接合表面处的交叠有效地置换表面污染物并有助于在没有热量输入的情况下接合表面之间的紧密接触。 密封装置可以包含药物制剂，生物传感器或MEMS装置。

公开(公告)号：WO2002103792A2

公开(公告)日：2002-12-27

申请号：PCT/IB2002/002305

申请日：2002-06-17

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  WEEKAMP, Johannus, W. ,  DE SAMBER, Marc, A. ,  DIJKEN, Durandus, K.

Inventor： WEEKAMP, Johannus, W. ,  DE SAMBER, Marc, A. ,  DIJKEN, Durandus, K.

IPC: H01L23/538

CPC classification number: H01L23/3107 ,  H01L21/56 ,  H01L23/051 ,  H01L23/66 ,  H01L25/0652 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/1423 ,  H01L2924/00014

Abstract: The invention relates to a method of manufacturing a semiconductor device (10), wherein a semiconductor element (1) provided with a number of connection regions (2) is fitted between a first, electroconductive plate (3) and a second plate (4), wherein two connection conductors (3A, 3B) are formed, from the first plate (3), for the two connection regions (2A, 2B) of the element (1), wherein a passivating encapsulation (5) is provided between the plates (3, 4) and around the element (1), and wherein the device (10) is formed by applying a mechanical separating technique in two mutually perpendicular directions (L, M). In a method according to the invention, the connection conductors (3A, 3B) are formed by providing a mask (6) on the first conducting plate (3) in such a manner that a part (3C) of the plate (3) situated between the connection regions (2A, 2B) remains exposed, which part is subsequently removed by etching. Such a method enables a very compact discrete or at least semi-discrete semiconductor device (10) to be readily obtained at low cost, while a high yield is achieved. In a preferred embodiment, also further parts (3D) of the conducting plate (3) situated at the location where the device (10) is to be sawn, cut or broken remain uncovered by the mask (6) and are removed during etching.

Abstract translation: 本发明涉及一种制造半导体器件（10）的方法，其中在第一导电板（3）和第二板（4）之间安装设有多个连接区域（2）的半导体元件（1） ，其中，对于所述元件（1）的两个连接区域（2A，2B），从所述第一板（3）形成两个连接导体（3A，3B），其中在所述板 （3）和所述元件（1）周围，并且其中所述装置（10）通过在两个相互垂直的方向（L，M）上施加机械分离技术而形成。 在根据本发明的方法中，连接导体（3A，3B）通过在第一导电板（3）上设置掩模（6）而形成，使得板（3）的部分（3C）位于 在连接区域（2A，2B）之间保持暴露，随后通过蚀刻去除该部分。 这种方法使得能够以低成本容易地获得非常紧凑的离散或至少半分立半导体器件（10），同时实现高产率。 在优选实施例中，位于设备（10）将被锯，切割或断裂的位置处的导电板（3）的另外的部分（3D）保持未被掩模（6）覆盖，并且在蚀刻期间被移除。

公开(公告)号：WO2015175554A3

公开(公告)日：2016-01-07

申请号：PCT/US2015030410

申请日：2015-05-12

Applicant: INVENSAS CORP

Inventor： KATKAR RAJESH ,  UZOH CYPRIAN EMEKA

IPC: H01L21/60 ,  H01L21/48 ,  H01L21/56 ,  H01L21/98 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L24/14 ,  B23K1/0016 ,  B23K3/0623 ,  B23K35/0244 ,  B23K35/0266 ,  B23K2201/40 ,  H01L21/02225 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/98 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/0333 ,  H01L2224/0391 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/051 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/06102 ,  H01L2224/10145 ,  H01L2224/11001 ,  H01L2224/11005 ,  H01L2224/11009 ,  H01L2224/111 ,  H01L2224/11318 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13078 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/1405 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75253 ,  H01L2224/81138 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8122 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/8385 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K1/115 ,  H05K1/144 ,  H05K3/341 ,  H05K2201/09572 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2224/81 ,  H01L2224/83

Abstract: In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion (510) of a solder ball's (140) surface is melted when the connection is formed on one structure (110) and/or when the connection is being attached to another structure (HOB). The structure (110) may be an integrated circuit, an interposer, a rigid or flexible wiring substrate, a printed circuit board, some other packaging substrate, or an integrated circuit package. In some embodiments, solder balls (140.1, 140.2) are joined by an intermediate solder ball (140i), upon melting of the latter only. Any of the solder balls (140, 140i) may have a non-solder central core (140C) coated by solder shell (140S). Some of the molten or softened solder may be squeezed out, to form a "squeeze-out" region (520, 520A, 520B, 520.1, 520.2). In some embodiments, a solder connection (210) such as discussed above, on a structure (110A), may be surrounded by a dielectric layer (1210), and may be recessed in a hole (1230) in that layer (1210), to help in aligning a post (1240) of a structure (HOB) with the connection (210) during attachment of the structures (110A, HOB). The dielectric layer (1210) may be formed by moulding. The dielectric layer may comprise a number of layers (1210.1, 1210.2), "shaved" (partially removed) to expose the solder connection (210). Alternatively, the recessed solder connections (210) may be formed using a sublimating or vapourisable material (1250), placed on top of the solder (210) before formation of the dielectric layer (1210) or coating solder balls (140); in the latter case, the solder (140C) sinks within the dielectric material (1210) upon removal of the material (1250) and subsequent reflow. The solder connections (210.1, 210.2) may be used for bonding one or more structures (HOB, HOC) (e.g. an integrated circuit die or wafer, a packaging substrate or a package) to a structure (110A) (a wiring substrate) on which a die (HOB) is flip-chip connected. The solder connections (210.1, 210.2) may differ from each other, in particular in height.

Abstract translation: 在一些实施例中，为了增加将不同结构与一个或多个焊球连接的焊料连接的高度与间距比，当焊接球（140）表面的一部分（510）形成在 一个结构（110）和/或当连接被附接到另一个结构（HOB）时。 结构（110）可以是集成电路，插入器，刚性或柔性布线基板，印刷电路板，一些其它封装基板或集成电路封装。 在一些实施例中，焊料球（140.1,140.2）仅在熔化时被中间焊球（140i）连接。 任何焊球（140,140i）可以具有由焊料壳（140S）涂覆的非焊料中心芯（140C）。 一些熔融或软化的焊料可能被挤出，以形成“挤出”区域（520,520A，520B，520.1,520.2）。 在一些实施例中，在结构（110A）上的如上所述的焊料连接（210）可被电介质层（1210）包围，并且可以凹入该层（1210）中的孔（1230）中， 以在结构（110A，110B）的附接期间帮助将结构的柱（1240）与连接件（210）对齐。 电介质层（1210）可以通过模塑形成。 介电层可以包括多个层（1210.1,1212.2），“剃光”（部分去除）以暴露焊料连接（210）。 或者，可以在形成电介质层（1210）或涂覆焊球（140）之前使用升华或蒸发的材料（1250）形成凹陷的焊料连接（210），放置在焊料（210）的顶部上。 在后一种情况下，当去除材料（1250）和随后的回流时，焊料（140C）在电介质材料（1210）内下沉。 焊接连接（210.1,210.2）可以用于将一个或多个结构（HOB，HOC）（例如集成电路管芯或晶片，封装衬底或封装）结合到结构（110A）（布线基板）上 一个芯片（HOB）是倒装芯片连接的。 焊接连接（210.1,210.2）可能彼此不同，特别是高度不同。

公开(公告)号：WO2013125086A1

公开(公告)日：2013-08-29

申请号：PCT/JP2012/075412

申请日：2012-10-01

Applicant: 日立化成株式会社

Inventor： 本田　一尊 ,  永井　朗 ,  佐藤　慎

IPC: H01L21/52 ,  B23K35/363 ,  C08L63/00 ,  H01L21/60 ,  H01L23/29 ,  H01L23/31

CPC classification number: C09J11/06 ,  B23K35/3613 ,  B23K35/3618 ,  B23K35/362 ,  C08K5/092 ,  C09J163/00 ,  H01L21/563 ,  H01L23/295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/03825 ,  H01L2224/0401 ,  H01L2224/051 ,  H01L2224/05111 ,  H01L2224/05116 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05575 ,  H01L2224/0558 ,  H01L2224/056 ,  H01L2224/05611 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11825 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13575 ,  H01L2224/1358 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/271 ,  H01L2224/27416 ,  H01L2224/27436 ,  H01L2224/27848 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/81011 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/81895 ,  H01L2224/81907 ,  H01L2224/831 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/9205 ,  H01L2224/92122 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H05K3/305 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/8385 ,  H01L2924/00 ,  C08L63/00 ,  H01L2224/27 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01029 ,  H01L2224/11 ,  H01L2924/0001

Abstract: 　エポキシ樹脂、硬化剤及び下記式（１）で表される基を有する化合物を含有する、半導体用接着剤。［式中、Ｒ １ は、電子供与性基を示す。］

Abstract translation: 提供一种含有环氧树脂，固化剂和具有式（1）所示基团的化合物的半导体粘合剂。 [式中，R1表示给电子基团]

公开(公告)号：WO2010022970A1

公开(公告)日：2010-03-04

申请号：PCT/EP2009/006258

申请日：2009-08-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  GRILLBERGER, Michael ,  LEHR, Matthias, Uwe

Inventor： GRILLBERGER, Michael ,  LEHR, Matthias, Uwe

IPC: H01L23/58 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/522 ,  H01L23/53295 ,  H01L23/562 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/051 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/16 ,  H01L2924/1433 ,  H01L2924/00014

Abstract: By dividing a single chip area into individual sub areas (200a, 200b, 200c on the basis of one or more stress relaxation regions 280a, 280b,) a thermally- induced stress in each of the sub areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip (200) may be used compared to conventional strategies.

Abstract translation: 通过将单个芯片区域划分成各个子区域（200a，200b，200c，基于一个或多个应力松弛区域280a，280b），每个子区域中的热诱导应力可以在复合集成 电路，从而提高包括低k电介质材料或ULK材料的复杂金属化系统的整体可靠性。 因此，与常规策略相比，可以使用大量堆叠的金属化层与半导体芯片（200）的增加的横向尺寸的组合。

公开(公告)号：WO2006093600A3

公开(公告)日：2007-02-15

申请号：PCT/US2006002682

申请日：2006-01-26

Applicant: INTEGRAL WAVE TECHNOLOGIES INC ,  AZRAI FIRAS ,  YATES MICHEAL ,  NELMS DAVID

Inventor： AZRAI FIRAS ,  YATES MICHEAL ,  NELMS DAVID

IPC: H01G9/00 ,  H02H7/16 ,  H02M3/07 ,  H02M3/335

CPC classification number: H02M3/07 ,  H01L23/3128 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/5223 ,  H01L25/18 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05026 ,  H01L2224/051 ,  H01L2224/05571 ,  H01L2224/056 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02M2001/009 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A plurality of trenched capacitors are grouped in phases. A control circuit switches each phase between charging and discharging states devised to supply one or more loads with controlled power.

Abstract translation: 多个沟槽电容器被分阶段分组。 控制电路切换充电和放电状态之间的每个相位，以设计为一个或多个负载提供受控电力。

公开(公告)号：WO2004061903A3

公开(公告)日：2005-04-14

申请号：PCT/US0339878

申请日：2003-12-16

Applicant: EASIC CORP

Inventor： OR-BACH ZVI ,  COOKE LAURENCE ,  APOSTOL ADRIAN ,  IACOBUT ROMEO

IPC: H01L20060101 ,  H01L21/44 ,  H01L21/60 ,  H01L23/31 ,  H01L23/34 ,  H01L23/485 ,  H01L27/10 ,  H01L27/118

CPC classification number: H01L28/20 ,  H01L23/3114 ,  H01L24/10 ,  H01L27/11803 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/051 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05005 ,  H01L2224/05541 ,  H01L2924/00014

Abstract: A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/Os (36) and also including the step of forming redistribution layer (32) for redistribution at least some of the Area I/Os for the purpose of the device packaging. The fabrication may utilize Direct Write e-Beam for customization. The customization step may include fabricating various types of devices at different volume from the same wafer.

Abstract translation: 提出了一种新颖的方法来为ASIC提供大幅降低的NRE和体积灵活性。 本发明包括一种制造集成电路的方法，包括以下步骤：提供半导体衬底，形成包括多个区域I / O（36）的无边界逻辑阵列，还包括形成再分配层（32）的步骤，用于 为了设备包装的目的，至少部分区域I / O重新分配。 该制造可以利用直接写电子束进行定制。 定制步骤可以包括制造与同一晶片不同体积的各种类型的装置。