公开(公告)号：WO2019055052A1

公开(公告)日：2019-03-21

申请号：PCT/US2017/052109

申请日：2017-09-18

Applicant: INTEL CORPORATION ,  GLASSMAN, Timothy E. ,  SEGHETE, Dragos ,  STRUTT, Nathan ,  ASURI, Namrata S. ,  GOLONZKA, Oleg

Inventor： GLASSMAN, Timothy E. ,  SEGHETE, Dragos ,  STRUTT, Nathan ,  ASURI, Namrata S. ,  GOLONZKA, Oleg

IPC: H01L45/00

Abstract: Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.

公开(公告)号：WO2019005167A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040510

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  STRUTT, Nathan ,  WU, Stephen Y. ,  ASURI, Namrata S. ,  GLASSMAN, Timothy E. ,  GOLONZKA, Oleg ,  MUKHERJEE, Niloy ,  SEGHETE, Dragos ,  WIEGAND, Christopher J.

Inventor： STRUTT, Nathan ,  WU, Stephen Y. ,  ASURI, Namrata S. ,  GLASSMAN, Timothy E. ,  GOLONZKA, Oleg ,  MUKHERJEE, Niloy ,  SEGHETE, Dragos ,  WIEGAND, Christopher J.

IPC: H01L45/00

CPC classification number: H01L45/08 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: An approach for integrating a resistive random access memory (RRAM) device on a dual bottom electrode layer is described. In an example, a resistive random access memory (RRAM) device includes a dual bottom electrode disposed above a substrate. The dual bottom electrode includes a first conductive layer disposed above a substrate, a second conductive layer disposed above the first conductive layer and an intermediate layer between the first conductive layer and the second conductive layer, where the intermediate layer includes oxygen. A switching layer is disposed on the dual bottom electrode layer. An oxygen exchange layer is disposed on the switching layer and a top electrode is disposed on the switching layer.

公开(公告)号：WO2019190502A1

公开(公告)日：2019-10-03

申请号：PCT/US2018/024866

申请日：2018-03-28

Applicant: INTEL CORPORATION ,  GLASSMAN, Timothy E. ,  STRUTT, Nathan ,  WU, Stephen Y. ,  CHEN, Albert ,  ASURI, Namrata S. ,  GOLONZKA, Oleg ,  SEGHETE, Dragos

Inventor： GLASSMAN, Timothy E. ,  STRUTT, Nathan ,  WU, Stephen Y. ,  CHEN, Albert ,  ASURI, Namrata S. ,  GOLONZKA, Oleg ,  SEGHETE, Dragos

IPC: H01L45/00

Abstract: A resistive random-access memory device comprises a transistor and a filmstack. The memory stack comprises a bottom electrode coupled to the transistor. A primary dielectric is formed over the bottom electrode. An oxygen exchange layer is formed on the primary dielectric. A top electrode is formed on the oxygen exchange layer. A secondary dielectric is formed between the primary dielectric and the bottom electrode to improve endurance cycling and to enable a lower switching voltage.

公开(公告)号：WO2016204771A1

公开(公告)日：2016-12-22

申请号：PCT/US2015/036519

申请日：2015-06-18

Applicant: INTEL CORPORATION

Inventor： CLENDENNING, Scott B. ,  MITAN, Martin M. ,  GLASSMAN, Timothy E. ,  GRIGGIO, Flavio ,  KLOSTER, Grant M. ,  FRASURE, Kent N. ,  GSTREIN, Florian ,  HOURANI, Rami

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L21/76879 ,  C23C16/045 ,  H01L21/28 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/31144 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76865 ,  H01L21/76876 ,  H01L29/66545 ,  H01L29/66795 ,  H01L2221/1063

Abstract: Bottom-up fill approaches for forming metal features of semiconductor structures, and the resulting structures, are described. In an example, a semiconductor structure includes a trench disposed in an inter-layer dielectric (ILD) layer. The trench has sidewalls, a bottom and a top. A U-shaped metal seed layer is disposed at the bottom of the trench and along the sidewalls of the trench but substantially below the top of the trench. A metal fill layer is disposed on the U-shaped metal seed layer and fills the trench to the top of the trench. The metal fill layer is in direct contact with dielectric material of the ILD layer along portions of the sidewalls of the trench above the U-shaped metal seed layer.

Abstract translation: 描述了用于形成半导体结构的金属特征的自底向上填充方法以及所得的结构。 在一个示例中，半导体结构包括设置在层间电介质（ILD）层中的沟槽。 沟槽有侧壁，底部和顶部。 U形金属种子层设置在沟槽的底部并且沿着沟槽的侧壁但基本上在沟槽的顶部下方。 金属填充层设置在U形金属种子层上，并将沟槽填充到沟槽的顶部。 金属填充层与U形金属种子层上方的沟槽的侧壁的部分直接接触ILD层的电介质材料。

公开(公告)号：WO2013089711A9

公开(公告)日：2013-06-20

申请号：PCT/US2011/064972

申请日：2011-12-14

Applicant: INTEL CORPORATION ,  LINDERT, Nick ,  GLASSMAN, Timothy E. ,  BARAN, Andre

Inventor： LINDERT, Nick ,  GLASSMAN, Timothy E. ,  BARAN, Andre

IPC: H01L27/108 ,  H01L21/8242

Abstract: Metal-insulator-metal (MIM) capacitors with insulator stacks having a plurality of metal oxide layers are described. For example, a MIM capacitor for a semiconductor device includes a trench disposed in a dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. An insulator stack is disposed above and conformal with the first metal plate. The insulator stack includes a first metal oxide layer having a first dielectric constant and a second metal oxide layer having a second dielectric constant. The first dielectric constant is higher than the second dielectric constant. The MIM capacitor also includes a second metal plate disposed above and conformal with the insulator stack.