公开(公告)号：WO2017123327A1

公开(公告)日：2017-07-20

申请号：PCT/US2016/063106

申请日：2016-11-21

Applicant: INTEL CORPORATION

Inventor： COX, Christopher E. ,  BAINS, Kuljit S. ,  VERGIS, George ,  NALE, Bill ,  MCCALL, James A. ,  ZHAO, Chong J. ,  SAH, Suneeta ,  VOGT, Pete D. ,  GOLES, John R.

IPC: G06F13/16

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1045 ,  G11C11/4096 ,  G11C14/0009

Abstract: Examples include techniques to access or operate a dual in-line memory module (DIMM) via one or multiple data channels. In some examples, memory devices at or on the DIMM may be accessed via one or more data channels. The one or more data channels arranged such that the DIMM is configured to operate in a dual channel mode that includes two data channels or to operate in a single channel mode that includes a single data channel.

Abstract translation: 示例包括通过一个或多个数据通道访问或操作双列直插式内存模块（DIMM）的技术。 在一些示例中，DIMM处或其上的存储器设备可以经由一个或多个数据通道来访问。 所述一个或多个数据通道被布置成使得DIMM被配置为以包括两个数据通道的双通道模式操作或者以包括单个数据通道的单通道模式操作。

公开(公告)号：WO2014105149A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/046897

申请日：2013-06-20

Applicant: INTEL CORPORATION

Inventor： MCCALL, James A. ,  BAINS, Kuljit S. ,  CONROW, Derek M. ,  MARTIN, Aaron

IPC: G06F1/26

CPC classification number: H03K19/0008 ,  G06F3/041 ,  G06F3/0412 ,  H03K19/0005 ,  H03K19/017509 ,  H03K19/017545

Abstract: An output driver includes control logic configured to switch on a pull-up circuit and a pull-down circuit to provide an output impedance for a logic low on a transmission line. The output driver includes a variable pull-up resistor. The control logic is configured to switch on the pull-up circuit to a first value of impedance to drive a logic high on the transmission line. The control logic is configured to switch on the pull-up circuit to a second value of impedance and to switch on the pull-down circuit to provide the output impedance to drive a logic low on the transmission line. The system could alternatively be configured for the inverse to switch on a combination of pull-up and pull-down circuits for a logic high, where the pull-down circuit is switched on for a logic low.

Abstract translation: 输出驱动器包括被配置为接通上拉电路和下拉电路以提供传输线路上的逻辑低电平的输出阻抗的控制逻辑。 输出驱动器包括一个可变上拉电阻。 控制逻辑被配置为将上拉电路接通到第一阻抗值，以驱动传输线上的逻辑高电平。 控制逻辑被配置为将上拉电路接通到第二阻抗值，并且接通下拉电路以提供输出阻抗以驱动传输线上的逻辑低电平。 可替代地，该系统可以被配置为反向以将逻辑高的上拉和下拉电路的组合打开，其中下拉电路被接通为逻辑低。

公开(公告)号：WO2014085266A1

公开(公告)日：2014-06-05

申请号：PCT/US2013/071532

申请日：2013-11-22

Applicant: INTEL CORPORATION ,  MCCALL, James A. ,  BAINS, Kuljit S.

Inventor： MCCALL, James A. ,  BAINS, Kuljit S.

IPC: G11C5/14 ,  G11C7/10

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G11C5/147 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/021 ,  G11C29/028

Abstract: Techniques and mechanisms for a memory device to concurrently receive and process signals each based on a different respective reference voltage level. In an embodiment, an input/output (I/O) interface of a memory device includes receiver circuits each to process a respective signal received via a corresponding signal line of a bus. In response to one or more configuration commands, a first receiver circuit is configured to process a first signal based on a first reference voltage level and a second receiver circuit is configured to process a second signal based on a second reference voltage level. In another embodiment, a memory controller sends the one or more configuration commands to such a memory device based on an evaluation of voltage swing characteristics each corresponding to a different respective signal line of a bus.

Abstract translation: 用于存储器件的技术和机制，用于基于不同的相应参考电压电平同时接收和处理信号。 在一个实施例中，存储器件的输入/输出（I / O）接口包括接收器电路，每个接收器电路用于处理经由总线的相应信号线接收的相应信号。 响应于一个或多个配置命令，第一接收器电路被配置为基于第一参考电压电平处理第一信号，并且第二接收器电路被配置为基于第二参考电压电平来处理第二信号。 在另一个实施例中，存储器控制器基于对每个对应于总线的不同相应信号线的电压摆动特性的评估将一个或多个配置命令发送到这种存储器设备。

公开(公告)号：WO2023282941A1

公开(公告)日：2023-01-12

申请号：PCT/US2022/021994

申请日：2022-03-25

Applicant: INTEL CORPORATION

Inventor： ZHAO, Chong J. ,  TOMISHIMA, Shigeki ,  BAINS, Kuljit S. ,  MCCALL, James A. ,  ZIAKAS, Dimitrios

IPC: G11C5/06

Abstract: An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respective ones of the fractions. The logic chip has a multiplexer. The multiplexer is to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.

公开(公告)号：WO2022093441A1

公开(公告)日：2022-05-05

申请号：PCT/US2021/051361

申请日：2021-09-21

Applicant: INTEL CORPORATION

Inventor： ZHAO, Chong J. ,  MCCALL, James A. ,  FRIAR, Robert J. ,  MEKONNEN, Yidnekachew S. ,  CHHAY, San K.

IPC: G11C5/06 ,  H05K5/02 ,  G11C8/18

Abstract: Examples described herein relate to a pattern of pins where the signals assigned to the pins are arranged in a manner to reduce cross-talk. In some examples, a socket substrate includes a first group of pins that includes a first group of data (DQ) pins separated by at least two Voltage Source Supply (VSS) pins from a second group of DQ pins and a third group of DQ pins separated by at least two VSS pins from a fourth group of DQ pins. In some examples, data strobe signal (DQS) pins are positioned in a column between the first and third groups of DQ pins and the second and fourth groups of DQ pins.

公开(公告)号：WO2014085267A1

公开(公告)日：2014-06-05

申请号：PCT/US2013/071533

申请日：2013-11-22

Applicant: INTEL CORPORATION ,  VERGIS, George ,  BAINS, Kuljit S. ,  MCCALL, James A. ,  CHANG, Ge

Inventor： VERGIS, George ,  BAINS, Kuljit S. ,  MCCALL, James A. ,  CHANG, Ge

IPC: G11C11/40

CPC classification number: G11C11/4074 ,  G06F3/0604 ,  G06F3/0637 ,  G06F3/0673 ,  G06F13/1663 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C7/109 ,  G11C8/06 ,  G11C11/408 ,  Y10T29/41

Abstract: Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC) package which includes a command and address bus and a plurality of memory chips each coupled thereto. Of the plurality of memory chips, only a first memory chip is operable to selectively provide termination to the command and address bus. Of the respective on-die termination control circuits of the plurality of memory chips, only the on-die termination control circuit of the first memory chip is coupled via any termination control signal line to any input/output (I/O) contact of the IC package. In another embodiment, the plurality of memory chips are configured in a series with one another, and wherein the first memory chip is located at an end of the series

Abstract translation: 用于为存储器件的多个芯片提供终端的技术和机制。 在一个实施例中，存储器件是集成电路（IC）封装，其包括命令和地址总线以及与其耦合的多个存储器芯片。 在多个存储器芯片中，只有第一存储器芯片可操作以选择性地提供对命令和地址总线的终止。 在多个存储器芯片的各个片上终端控制电路中，仅第一存储器芯片的片上终端控制电路经由任何终端控制信号线耦合到任何输入/输出（I / O）触点 IC封装。 在另一个实施例中，多个存储器芯片彼此串联配置，并且其中第一存储器芯片位于该系列的一端

公开(公告)号：WO2022178814A1

公开(公告)日：2022-09-01

申请号：PCT/CN2021/078102

申请日：2021-02-26

Applicant: INTEL CORPORATION ,  WANG, Wenzhi ,  YE, Xiaoning ,  CHU, Yunhui ,  YE, Chunfei ,  MCCALL, James A.

Inventor： WANG, Wenzhi ,  YE, Xiaoning ,  CHU, Yunhui ,  YE, Chunfei ,  MCCALL, James A.

IPC: H01P3/08 ,  H01L23/485 ,  H05K3/00 ,  H05K1/09

Abstract: Disclosed herein are integrated circuit (IC) supports with microstrips, and related embodiments. For example, an IC support may include a plurality of microstrips and a plurality of conductive segments. Individual ones of the conductive segments may be at least partially over at least two microstrips, a dielectric material may be between the plurality of microstrips and the plurality of conductive segments, and the conductive segments are included in a tape.

公开(公告)号：WO2017142664A1

公开(公告)日：2017-08-24

申请号：PCT/US2017/013799

申请日：2017-01-17

Applicant: INTEL CORPORATION

Inventor： MANSURI, Mozhgan ,  MARTIN, Aaron ,  MCCALL, James A.

IPC: G11C11/4076 ,  G11C7/22 ,  H03K3/03 ,  G05F1/575

CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/4234 ,  G11C7/10 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4093 ,  H03K5/14 ,  H03K2005/00052 ,  H04L7/0337

Abstract: Described is an apparatus which comprises: a comparator to be clocked by a clock signal to be provided by a clocking circuit, wherein the clocking circuit includes: a voltage controlled delay line having two or more delay cells; a multiplexer coupled to the voltage controlled delay line and operable to configure the clocking circuit as a ring oscillator with the voltage controlled delay line forming at least one delay section of the ring oscillator; and select logic coupled to the multiplexer, the select logic is to receive a signal indicating arrival of an input clock, and is to control the multiplexer according to the indication. Described is also an apparatus which comprises: a data path to receive input data; and a clock path to receive an input clock and to provide a preconditioned clock to the data path when the input clock is absent.

Abstract translation: 描述了一种装置，包括：由时钟电路提供的时钟信号计时的比较器，其中时钟电路包括：具有两个或更多个延迟单元的电压控制延迟线; 多路复用器，其耦合到所述电压控制延迟线，并且可操作以将所述时钟电路配置为环形振荡器，所述电压控制延迟线形成所述环形振荡器的至少一个延迟部分; 并选择耦合到所述多路复用器的逻辑，所述选择逻辑将接收指示输入时钟到达的信号，并且根据所述指示来控制所述多路复用器。 还描述了一种装置，其包括：接收输入数据的数据路径; 和一个时钟路径，用于接收输入时钟，并在输入时钟不存在时为数据路径提供预处理时钟。

公开(公告)号：WO2015047352A1

公开(公告)日：2015-04-02

申请号：PCT/US2013/062474

申请日：2013-09-27

Applicant: INTEL CORPORATION ,  BAINS, Kuljit ,  MCCALL, James A.

Inventor： BAINS, Kuljit ,  MCCALL, James A.

IPC: G06F13/00 ,  G06F12/00

CPC classification number: G06F13/4243 ,  G06F3/0635 ,  G06F12/14

Abstract: Provided are a device, system, and method for mapping memory controller connectors to memory connectors. A memory is programmed to transmit for each of a plurality of the memory data connectors, a pattern on the memory data connectors that has a first value for a selected memory data connector of the memory data connectors and a different value from the first value for the memory data connectors other than the selected memory data connector. For each of the memory data connectors, a read command is issued to read the pattern on the memory data connectors. a device data connector receiving the first value in the read pattern is mapped to the selected memory data connector transmitting the first value.

Abstract translation: 提供了一种用于将存储器控制器连接器映射到存储器连接器的装置，系统和方法。 存储器被编程为针对多个存储器数据连接器中的每一个进行传输，存储器数据连接器上的图案具有用于存储器数据连接器的所选择的存储器数据连接器的第一值和与用于存储器数据连接器的第一值不同的值 存储器数据连接器，而不是所选存储器数据连接器。 对于每个存储器数据连接器，发出读取命令以读取存储器数据连接器上的模式。 接收读取模式中的第一值的设备数据连接器被映射到发送第一值的所选择的存储器数据连接器。

公开(公告)号：WO2018125499A1

公开(公告)日：2018-07-05

申请号：PCT/US2017/063804

申请日：2017-11-29

Applicant: INTEL CORPORATION

Inventor： MCCALL, James A. ,  ZHANG, Zhichao ,  LI, Qin ,  LI, Xiang ,  DREW, John R.

IPC: G11C5/04 ,  H05K1/18 ,  H01R12/71

Abstract: Devices include a connecting card that may be used in a memory connector. The connecting card may include a substrate including a first substrate region and a second substrate region, a plurality of adjacent signal pathways extending from the first substrate region to the second substrate region, and a capacitor positioned between each of the adjacent signal pathways. Other embodiments are described and claimed.