公开(公告)号：WO2018063722A1

公开(公告)日：2018-04-05

申请号：PCT/US2017/049457

申请日：2017-08-30

Applicant: INTEL CORPORATION

Inventor： NACHIMUTHU, Murugasamy K. ,  KUMAR, Mohan J. ,  ZIAKAS, Dimitrios

IPC: G06F13/38 ,  G06F12/06

CPC classification number: G06F12/10 ,  G06F12/0284 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/0653 ,  G06F12/109 ,  G06F2212/1024 ,  G06F2212/217

Abstract: Provided are a method, apparatus, and a system in which an initiator node is configured to communicate with a target node that is coupled to a memory. At system initialization time, a memory address map of the initiator node is generated to include addresses corresponding to the memory to which the target node is coupled. The initiator node accesses the memory coupled to the target node, by using the memory address map of the initiator node.

Abstract translation: 提供了一种方法，设备和系统，其中启动器节点被配置为与耦合到存储器的目标节点进行通信。 在系统初始化时，生成启动器节点的存储器地址映射以包括与目标节点耦合到的存储器相对应的地址。 发起者节点通过使用发起者节点的存储器地址映射来访问耦合到目标节点的存储器。

公开(公告)号：WO2017112076A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/058879

申请日：2016-10-26

Applicant: INTEL CORPORATION

Inventor： AOKI, Russell S. ,  THIBADO, Jonathan W. ,  SMALLEY, Jeffory L. ,  LLAPITAN, David J. ,  BOYD, Thomas A. ,  KOFSTAD, Harvey R. ,  ZIAKAS, Dimitrios ,  YAN, Hongfei

IPC: H01R12/71 ,  H01R4/02 ,  H05K3/32

CPC classification number: H01L23/345 ,  H01L23/49816 ,  H01L23/49822 ,  H05K1/0212 ,  H05K1/141 ,  H05K1/144 ,  H05K3/3436 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2203/176

Abstract: A rework grid array interposer with direct power is described. The interposer has a foundation layer mountable between a motherboard and a package. A heater is embedded in the foundation layer to provide local heat to reflow solder to enable at least one of attachment or detachment of the package. A connector is mounted on the foundation layer and coupled to the heater and to the package to provide a connection path directly with the power supply and not via the motherboard. One type of interposer interfaces with a package having a solderable extension. Another interposer has a plurality of heater zones embedded in the foundation layer.

Abstract translation: 描述了具有直接功率的返工栅格阵列中介层。 内插器具有可安装在主板和封装之间的基础层。 加热器嵌入在基层中以提供局部热量来回流焊料，以使得封装的附接或分离中的至少一个能够进行。 连接器安装在基础层上并连接到加热器和封装，以提供直接与电源连接的连接路径而不是通过主板。 一种类型的内插器与具有可焊接扩展的封装件接合。 另一个插入器具有多个嵌入基础层中的加热器区域。

公开(公告)号：WO2013101201A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/068151

申请日：2011-12-30

Applicant: INTEL CORPORATION ,  ZIAKAS, Dimitrios ,  CAI, Zhong-Ning

Inventor： ZIAKAS, Dimitrios ,  CAI, Zhong-Ning

IPC: G06F12/00 ,  G06F13/14 ,  G06F13/16

CPC classification number: G06F3/0619 ,  G06F3/0646 ,  G06F3/0683 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0811 ,  G06F2212/1028 ,  G06F2212/205 ,  Y02D10/13

Abstract: Systems and methods to implement a multi-level memory system having a volatile memory and a non-volatile memory are implemented. A home agent may control memory access to both a volatile main memory and a non-volatile second level memory. The second level memory may be inclusive of the main memory. In an embodiment, the home agent may be configured to manage the memory system in a low power state. In a low power state, the volatile memory may be shut down and the non-volatile memory utilized as the only local memory. In an embodiment, the home agent may be configured to manage error recovery for the main memory by recovering the data saved locally in the second level memory. In an embodiment, multiple cores may access the second level memory.

Abstract translation: 实现具有易失性存储器和非易失性存储器的多级存储器系统的系统和方法。 归属代理可以控制对易失性主存储器和非易失性第二级存储器的存储器访问。 第二级存储器可以包括主存储器。 在一个实施例中，归属代理可以被配置为在低功率状态下管理存储器系统。 在低功率状态下，可以关闭易失性存储器，并将非易失性存储器用作唯一的本地存储器。 在一个实施例中，归属代理可以被配置为通过恢复在本地保存在第二级存储器中的数据来管理主存储器的错误恢复。 在一个实施例中，多个核可以访问第二级存储器。

公开(公告)号：WO2023282941A1

公开(公告)日：2023-01-12

申请号：PCT/US2022/021994

申请日：2022-03-25

Applicant: INTEL CORPORATION

Inventor： ZHAO, Chong J. ,  TOMISHIMA, Shigeki ,  BAINS, Kuljit S. ,  MCCALL, James A. ,  ZIAKAS, Dimitrios

IPC: G11C5/06

Abstract: An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respective ones of the fractions. The logic chip has a multiplexer. The multiplexer is to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.

公开(公告)号：WO2018017905A1

公开(公告)日：2018-01-25

申请号：PCT/US2017/043182

申请日：2017-07-20

Applicant: INTEL CORPORATION

Inventor： KUMAR, Mohan J. ,  NACHIMUTHU, Murugasamy K. ,  GORIUS, Aaron ,  ADILETTA, Matthew J. ,  WILDE, Myles ,  CROCKER, Michael ,  ZIAKAS, Dimitrios

IPC: G06F17/30 ,  G06F13/40

Abstract: Techniques for automated data center maintenance are described. In an example embodiment, an automated maintenance device may comprise processing circuitry and non- transitory computer-readable storage media comprising instructions for execution by the processing circuitry to cause the automated maintenance device to receive an automation command from an automation coordinator for a data center, identify an automated maintenance procedure based on the received automation command, and perform the identified automated maintenance procedure. Other embodiments are described and claimed.

Abstract translation: 描述了自动化数据中心维护的技术。 在示例实施例中，自动维护设备可以包括处理电路和非暂时性计算机可读存储介质，所述处理电路和非暂时性计算机可读存储介质包括用于由处理电路执行以使自动维护设备从数据中心的自动化协调器接收自动化命令的指令， 基于接收到的自动化命令识别自动维护过程，并执行识别的自动维护过程。 描述并要求保护其他实施例。

公开(公告)号：WO2015080717A1

公开(公告)日：2015-06-04

申请号：PCT/US2013/072159

申请日：2013-11-27

Applicant: INTEL CORPORATION ,  ZIAKAS, Dimitrios ,  COURY, Bassam N. ,  KUMAR, Mohan J. ,  NACHIMUTHU, Murugasamy K. ,  DANG, Thi ,  WUNDERLICH, Russell J.

Inventor： ZIAKAS, Dimitrios ,  COURY, Bassam N. ,  KUMAR, Mohan J. ,  NACHIMUTHU, Murugasamy K. ,  DANG, Thi ,  WUNDERLICH, Russell J.

IPC: G06F15/76

CPC classification number: G06F15/7803 ,  G06F11/1662 ,  G06F2201/805

Abstract: Systems and methods of implementing server architectures that can facilitate the servicing of memory components in computer systems. The systems and methods employ nonvolatile memory/storage modules that include nonvolatile memory (NVM) that can be used for system memory and mass storage, as well as firmware memory. The respective NVM/storage modules can be received in front or rear-loading bays of the computer systems. The systems and methods further employ single, dual, or quad socket processors, in which each processor is communicably coupled to at least some of the NVM/storage modules disposed in the front or rear-loading bays by one or more memory and/or input/output (I/O) channels. By employing NVM/storage modules that can be received in front or rear-loading bays of computer systems, the systems and methods provide memory component serviceability heretofore unachievable in computer systems implementing conventional server architectures.

Abstract translation: 实现服务器架构的系统和方法可以方便计算机系统中的存储器组件的维护。 这些系统和方法采用非易失性存储/存储模块，其中包括可用于系统内存和大容量存储的非易失性存储器（NVM）以及固件存储器。 相应的NVM /存储模块可以被接收在计算机系统的前部或后部装载槽中。 该系统和方法进一步采用单插槽，双插槽或四插槽处理器，其中每个处理器通过一个或多个存储器和/或输入可通信地耦合到布置在前装载或后装载槽中的至少一些NVM /存储模块 /输出（I / O）通道。 通过采用可以在计算机系统的前端或后端加载的接收的NVM /存储模块，系统和方法提供了迄今为止在实现常规服务器架构的计算机系统中无法实现的存储器组件的可维护性。

公开(公告)号：WO2016048553A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/046901

申请日：2015-08-26

Applicant: INTEL CORPORATION

Inventor： PRAKASH, Mani ,  PAYTON, Edward L. ,  GROOMS, John K. ,  ZIAKAS, Dimitrios ,  ARAFA, Mohamed ,  RAMANUJAN, Raj K. ,  WANG, Dong

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G11C14/0018 ,  G11C5/04 ,  G11C7/1072 ,  G11C11/40615

Abstract: Memory modules, controllers, and electronic devices comprising memory modules are described. In one embodiment, a memory module comprises a nonvolatile memory and an interface to a volatile memory bus, at least one input power rail to receive power from a host platform, and a controller comprising logic, at least partially including hardware logic, to convert the power from the input power rail from an input voltage to at least one output voltage, different from the input voltage. Other embodiments are also disclosed and claimed.

Abstract translation: 描述了包括存储器模块的存储器模块，控制器和电子设备。 在一个实施例中，存储器模块包括非易失性存储器和到易失性存储器总线的接口，至少一个用于从主机平台接收电力的输入电源轨，以及控制器，其包括至少部分地包括硬件逻辑的逻辑，以将 从输入电源轨从输入电压到不同于输入电压的至少一个输出电压的电力。 还公开并要求保护其他实施例。

公开(公告)号：WO2013100939A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067496

申请日：2011-12-28

Applicant: INTEL CORPORATION ,  NACHIMUTHU, Murugasamy, K. ,  KUMAR, Mohan, J. ,  DAS, Debaleena ,  ZIAKAS, Dimitrios

Inventor： NACHIMUTHU, Murugasamy, K. ,  KUMAR, Mohan, J. ,  DAS, Debaleena ,  ZIAKAS, Dimitrios

IPC: G11C29/42 ,  G11C13/02

CPC classification number: G06F11/1044 ,  G06F11/1064 ,  G11C5/04 ,  G11C13/0004

Abstract: In accordance with some embodiments, memory modules containing phase change memory elements may be organized so that each memory integrated circuit includes both data and error correcting code. As a result of including the error correcting code in each integrated circuit, extra accesses of the memory module to extract the error correcting code can be avoided, improving the performance of the overall memory module in some embodiments.

Abstract translation: 根据一些实施例，可以组织包含相变存储器元件的存储器模块，使得每个存储器集成电路都包括数据和纠错码。 作为在每个集成电路中包括纠错码的结果，可以避免存储器模块提取错误校正码的额外访问，从而在一些实施例中提高整个存储器模块的性能。

公开(公告)号：WO2013048500A1

公开(公告)日：2013-04-04

申请号：PCT/US2011/054436

申请日：2011-09-30

Applicant: INTEL CORPORATION ,  RAMANUJAN, Raj, K. ,  ZIAKAS, Dimitrios ,  ZIMMERMAN, David, J. ,  KUMAR, Mohan, J. ,  SWAMINATHAN, Muthukumar, P. ,  COURY, Bassam, N.

Inventor： RAMANUJAN, Raj, K. ,  ZIAKAS, Dimitrios ,  ZIMMERMAN, David, J. ,  KUMAR, Mohan, J. ,  SWAMINATHAN, Muthukumar, P. ,  COURY, Bassam, N.

IPC: G06F13/14 ,  G06F12/00

CPC classification number: G06F12/0811 ,  G06F12/0238 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/0848 ,  G06F12/0866 ,  G06F12/0897 ,  G06F13/1684 ,  G06F2212/2024 ,  G06F2212/304

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as "far memory." Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as "near memory."

Abstract translation: 描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。 在一个实施例中，PCMS存储器件被用作层次结构中的一个层，有时被称为“远存储器”。 更高性能的存储器件，例如放置在远存储器之前的DRAM，并用于掩盖远存储器的一些性能限制。 这些更高性能的存储器件被称为“接近存储器”。

公开(公告)号：WO2013048497A1

公开(公告)日：2013-04-04

申请号：PCT/US2011/054430

申请日：2011-09-30

Applicant: INTEL CORPORATION ,  RAMANUJAN, Raj, K. ,  AGARWAL, Rajat ,  CHENG, Kai ,  POLEPEDDI, Taarinya ,  RAAD, Camille, C. ,  ZIMMERMAN, David, J. ,  SWAMINATHAN, Muthukumar, P. ,  ZIAKAS, Dimitrios ,  KUMAR, Mohan, J.

Inventor： RAMANUJAN, Raj, K. ,  AGARWAL, Rajat ,  CHENG, Kai ,  POLEPEDDI, Taarinya ,  RAAD, Camille, C. ,  ZIMMERMAN, David, J. ,  SWAMINATHAN, Muthukumar, P. ,  ZIAKAS, Dimitrios ,  KUMAR, Mohan, J.

IPC: G06F12/00 ,  G11C7/10

CPC classification number: G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/2024 ,  G06F2212/205 ,  G11C11/40615 ,  G11C14/009 ,  Y02D10/13

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as "far memory." Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as "near memory."

Abstract translation: 描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。 在一个实施例中，PCMS存储器件被用作层次结构中的一个层，有时被称为“远存储器”。 更高性能的存储器件，例如放置在远存储器之前的DRAM，并用于掩盖远存储器的一些性能限制。 这些更高性能的存储器件被称为“接近存储器”。