公开(公告)号：WO2019005154A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040490

申请日：2017-06-30

Applicant: INTEL CORPORATION

Inventor： THANU, Dinesh Padmanabhan Ramalekshmi ,  DHAVALESWARAPU, Hemanth K. ,  GUTHIKONDA, Venkata Suresh ,  BEATTY, John J. ,  AN, Yonghao ,  AYALA, Marco Aurelio Cartas ,  GARNER, Luke J. ,  PENG, Li

IPC: H01L23/40 ,  H01L23/36 ,  H01L23/482 ,  H01L25/065

CPC classification number: H01L23/16 ,  H01L23/3675 ,  H01L23/42 ,  H01L23/482 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.