公开(公告)号：WO2022094587A1

公开(公告)日：2022-05-05

申请号：PCT/US2021/072096

申请日：2021-10-28

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： UZOH, Cyprian, Emeka

IPC: H01L23/00

Abstract: A bonding method can include polishing a first bonding layer of a first element for direct bonding, the first bonding layer comprises a first conductive pad and a first non-conductive bonding region. After the polishing, a last chemical treatment can be performed on the polished first bonding layer. After performing the last chemical treatment, the first bonding layer of the first element can be directly bonded to a second bonding layer of a second element without an intervening adhesive, including directly bonding the first conductive pad to a second conductive pad of the second bonding layer and directly bonding the first non-conductive bonding region to a second nonconductive bonding region of the second bonding layer. No treatment or rinse is performed on the first bonding layer between performing the last chemical treatment and directly bonding.

公开(公告)号：WO2018194827A1

公开(公告)日：2018-10-25

申请号：PCT/US2018/025694

申请日：2018-04-02

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： UZOH, Cyprian, Emeka

IPC: H01L21/78 ,  H01L21/56 ,  H01L21/76 ,  H01L21/67 ,  H01L25/065 ,  H01L23/48

Abstract: Representative implementations provide techniques and systems for processing integrated circuit (IC) dies. Dies being prepared for intimate surface bonding (to other dies, to substrates, to another surface, etc.) may be processed with a minimum of handling, to prevent contamination of the surfaces or the edges of the dies. The techniques include processing dies while the dies are on a dicing sheet or other device processing film or surface. Systems include integrated cleaning components arranged to perform multiple cleaning processes simultaneously.

公开(公告)号：WO2018118488A1

公开(公告)日：2018-06-28

申请号：PCT/US2017/065601

申请日：2017-12-11

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： UZOH, Cyprian, Emeka

IPC: H01L23/32 ,  H01L25/16 ,  H01L25/065

CPC classification number: H01L21/67336 ,  H01L21/02076 ,  H01L21/67333 ,  H01L24/75 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/7501 ,  H01L2224/7525 ,  H01L2224/7565 ,  H01L2224/7598 ,  H01L2224/83012 ,  H01L2224/83013 ,  H01L2224/83896 ,  H01L2224/83948

Abstract: Representative implementations of devices and techniques provide a device and a technique for processing integrated circuit (IC) dies. The device comprises a die tray (such as a pick and place tray, for example) for holding the dies during processing. The die tray may include an array of pockets sized to hold individual dies. The technique can include loading dies on the die tray, cleaning the top and bottom surfaces of the dies, and ashing and activating both surfaces of the dies while on the die tray, eliminating the need to turn the dies over during processing.

公开(公告)号：WO2022147460A1

公开(公告)日：2022-07-07

申请号：PCT/US2021/073170

申请日：2021-12-29

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： KATKAR, Rajesh ,  HABA, Belgacem ,  ENQUIST, Paul, M. ,  FOUNTAIN, Gaius, Gillman, Jr. ,  GAO, Guilian ,  UZOH, Cyprian, Emeka

IPC: H01L23/00 ,  H01L25/16 ,  H01L25/00

Abstract: Embodiments of methods for producing direct bonded structures and methods for forming direct bonded structures are disclosed. The direct bonded structures may include elements comprising active electronics, microelectromechanical systems, optical elements, and so forth.

公开(公告)号：WO2018125673A3

公开(公告)日：2018-07-05

申请号：PCT/US2017/067304

申请日：2017-12-19

Applicant: INVENSAS BONDING TECHNOLOGIES, INC

Inventor： UZOH, Cyprian, Emeka ,  GAO, Guilian

IPC: H01L21/768

Abstract: Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.

公开(公告)号：WO2018125673A2

公开(公告)日：2018-07-05

申请号：PCT/US2017/067304

申请日：2017-12-19

Applicant: INVENSAS BONDING TECHNOLOGIES, INC

Inventor： UZOH, Cyprian, Emeka ,  GAO, Guilian

IPC: H01L21/768

Abstract: Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.

公开(公告)号：WO2022147429A1

公开(公告)日：2022-07-07

申请号：PCT/US2021/073122

申请日：2021-12-27

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： FOUNTAIN, Gaius, Gillman, Jr. ,  UZOH, Cyprian, Emeka ,  HUDSON, George, Carlton ,  POSTHILL, John

IPC: H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

公开(公告)号：WO2022094579A1

公开(公告)日：2022-05-05

申请号：PCT/US2021/072083

申请日：2021-10-28

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： GAO, Guilian ,  UZOH, Cyprian, Emeka ,  MIRKARIMI, Laura, Wills ,  FOUNTAIN, JR., Gaius, Gillman

IPC: H01L23/00

Abstract: A bonding method can include activating a first bonding layer of a first element for direct bonding to a second bonding layer of a second element. The bonding method can include, after the activating, providing a protective layer over the activated first bonding layer of the first element.

公开(公告)号：WO2022212596A1

公开(公告)日：2022-10-06

申请号：PCT/US2022/022677

申请日：2022-03-30

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： UZOH, Cyprian, Emeka ,  WORKMAN, Thomas

IPC: H01L23/00 ,  H01L2224/03009 ,  H01L2224/038 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/80004 ,  H01L2224/80009 ,  H01L2224/80031 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80905 ,  H01L2224/94 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L2924/095

Abstract: Disclosed herein are methods for direct bonding. In some embodiments, a direct bonding method comprises preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; and after the preparing, providing a protective layer over the prepared first bonding surface of the first element, the protective layer having a thickness less than 3 microns.

公开(公告)号：WO2022147459A1

公开(公告)日：2022-07-07

申请号：PCT/US2021/073169

申请日：2021-12-29

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： UZOH, Cyprian, Emeka

IPC: H01L23/00

Abstract: An element is disclosed. The element can include a non-conductive structure having a non-conductive bonding surface, a cavity at least partially extending through a portion of a thickness of the non-conductive structure from the non-conductive bonding surface, and a conductive pad disposed in the cavity. The cavity has a bottom side and a sidewall. The conductive pad has a bonding surface and a back side opposite the bonding surface. An average size of the grains at the bonding surface is smaller than an average size of the grains adjacent the bottom side of the cavity. The conductive pad can include a crystal structure with grains oriented along a 111 crystal plane. The element can be bonded to another element to form a bonded structure. The element and the other element can be directly bonded to one another without an intervening adhesive.