公开(公告)号：WO2017015432A1

公开(公告)日：2017-01-26

申请号：PCT/US2016/043266

申请日：2016-07-21

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Inventor： OLIVER, William, D. ,  DAS, Rabindra, N. ,  HOVER, David, J. ,  ROSENBERG, Danna ,  MILOSHI, Xhovalin ,  BOLKHOVSKY, Vladimir ,  YODER, Jonilyn, L. ,  STULL, Corey, W. ,  GOUKER, Mark, A.

IPC: H01P7/00 ,  H01L39/14 ,  H01L39/02

CPC classification number: H01L39/2493 ,  G06N99/002 ,  H01L27/18 ,  H01L39/223 ,  H01L39/2416 ,  H01P7/086

Abstract: A superconducting integrated circuit includes at least one superconducting resonator, including a substrate, a conductive layer disposed over a surface of the substrate with the conductive layer including at least one conductive material including a substantially low stress polycrystalline Titanium Nitride (TiN) material having an internal stress less than about two hundred fifty MPa (magnitude) such that the at least one superconducting resonator and/or qubit (hereafter called "device") is provided as a substantially high quality factor, low loss superconducting device.

Abstract translation: 超导集成电路包括至少一个超导谐振器，包括衬底，设置在衬底的表面上的导电层，导电层包括至少一个导电材料，导电材料包括具有内部的基本上低应力的多晶氮化钛（TiN）材料 应力小于约二百五十兆帕（大小），使得至少一个超导谐振器和/或量子比特（以下称为“器件”）被提供为基本上高质量因子的低损耗超导装置。

公开(公告)号：WO2017131831A2

公开(公告)日：2017-08-03

申请号：PCT/US2016/060343

申请日：2016-11-03

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Inventor： OLIVER, William, D. ,  KERMAN, Andrew, J. ,  DAS, Rabindra, N. ,  YOST, Donna-Ruth, W. ,  ROSENBERG, Danna ,  GOUKER, Mark, A.

IPC: H01L39/04 ,  H01L23/498

CPC classification number: H01L27/18 ,  B82Y10/00 ,  G06N99/002 ,  H01L21/02063 ,  H01L21/02282 ,  H01L21/02345 ,  H01L22/26 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L39/02 ,  H01L39/025 ,  H01L39/223 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05111 ,  H01L2224/05116 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0558 ,  H01L2224/05609 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/08503 ,  H01L2224/11001 ,  H01L2224/11005 ,  H01L2224/1111 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/117 ,  H01L2224/11902 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/80896 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: Quantum bit (qubit) circuits, coupler circuit structures and coupling techniques are described. Such circuits and techniques may be used to provide multi-qubit circuits suitable for use in multichip modules (MCMs).

Abstract translation: 描述量子位（量子位）电路，耦合器电路结构和耦合技术。 这种电路和技术可以用于提供适用于多芯片模块（MCM）的多量子位电路。

公开(公告)号：WO2017131831A3

公开(公告)日：2017-08-03

申请号：PCT/US2016/060343

申请日：2016-11-03

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Inventor： OLIVER, William, D. ,  KERMAN, Andrew, J. ,  DAS, Rabindra, N. ,  YOST, Donna-Ruth, W. ,  ROSENBERG, Danna ,  GOUKER, Mark, A.

IPC: H01L23/538 ,  H01L39/04

Abstract: Quantum bit (qubit) circuits, coupler circuit structures and coupling techniques are described. Such circuits and techniques may be used to provide multi-qubit circuits suitable for use in multichip modules (MCMs).

公开(公告)号：WO2017079424A1

公开(公告)日：2017-05-11

申请号：PCT/US2016/060309

申请日：2016-11-03

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Inventor： OLIVER, William, D. ,  KERMAN, Andrew, J. ,  DAS, Rabindra, N. ,  YOST, Donna-Ruth, W. ,  ROSENBERG, Danna ,  GOUKER, Mark, A.

IPC: H01L23/48 ,  H01L23/538 ,  H01L39/04

CPC classification number: H01L27/18 ,  B82Y10/00 ,  G06N99/002 ,  H01L21/02063 ,  H01L21/02282 ,  H01L21/02345 ,  H01L22/26 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L39/02 ,  H01L39/025 ,  H01L39/223 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05111 ,  H01L2224/05116 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0558 ,  H01L2224/05609 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/08503 ,  H01L2224/11001 ,  H01L2224/11005 ,  H01L2224/1111 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/117 ,  H01L2224/11902 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/80896 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: Described are concepts, systems, circuits and techniques related to shielded through via structures and methods for fabricating such shielded through via structures. The described shielded through via structures and techniques allow for assembly of multi-layer semiconductor structures including one or more superconducting semiconductor structures (or integrated circuits).

Abstract translation: 描述了涉及屏蔽通孔结构的概念，系统，电路和技术以及制造这种屏蔽通孔结构的方法。 所描述的屏蔽式通孔结构和技术允许组装包括一个或多个超导半导体结构（或集成电路）的多层半导体结构。

公开(公告)号：WO2017079417A1

公开(公告)日：2017-05-11

申请号：PCT/US2016/060296

申请日：2016-11-03

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Inventor： OLIVER, William, D. ,  KERMAN, Andrew, J. ,  DAS, Rabindra, N. ,  YOST, Donna-Ruth, W. ,  ROSENBERG, Danna ,  GOUKER, Mark, A.

IPC: H01L21/312 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/482 ,  H01L23/538

CPC classification number: H01L27/18 ,  B82Y10/00 ,  G06N99/002 ,  H01L21/02063 ,  H01L21/02282 ,  H01L21/02345 ,  H01L22/26 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L39/02 ,  H01L39/025 ,  H01L39/223 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05111 ,  H01L2224/05116 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0558 ,  H01L2224/05609 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/08503 ,  H01L2224/11001 ,  H01L2224/11005 ,  H01L2224/1111 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/117 ,  H01L2224/11902 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/80896 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

Abstract translation: 多层半导体结构包括第一半导体结构和第二半导体结构，其中第一和第二半导体结构中的至少一个被设置为超导半导体结构。 多层半导体结构还包括一个或多个互连结构。 每个互连结构设置在第一和第二半导体结构之间并且耦合到设置在第一和第二半导体结构上的相应的互连焊盘。 另外，每个互连结构包括多个互连部分。 至少一个互连部分包括至少一个超导材料和/或部分超导材料。

公开(公告)号：WO2017079394A1

公开(公告)日：2017-05-11

申请号：PCT/US2016/060263

申请日：2016-11-03

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Inventor： OLIVER, William, D. ,  KERMAN, Andrew, J. ,  DAS, Rabindra, N. ,  YOST, Donna-Ruth, W. ,  ROSENBERG, Danna ,  GOUKER, Mark, A.

IPC: H01L21/312 ,  H01L21/44 ,  H01L21/4763 ,  H01L23/482 ,  H01L23/538

CPC classification number: H01L27/18 ,  B82Y10/00 ,  G06N99/002 ,  H01L21/02063 ,  H01L21/02282 ,  H01L21/02345 ,  H01L22/26 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L39/02 ,  H01L39/025 ,  H01L39/223 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05111 ,  H01L2224/05116 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0558 ,  H01L2224/05609 ,  H01L2224/05644 ,  H01L2224/06181 ,  H01L2224/08503 ,  H01L2224/11001 ,  H01L2224/11005 ,  H01L2224/1111 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/117 ,  H01L2224/11902 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/80896 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06531 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A method of fabricating an interconnect structure includes providing a semiconductor structure and performing a first spin resist and bake cycle. The first spin resist and bake cycle includes applying a first predetermined amount of a resist material over one or more portions of the semiconductor structure and baking the semiconductor structure to form a first resist layer portion of a resist layer. The method also includes performing a next spin resist and bake cycle. The next spin resist and bake cycle includes applying a next predetermined amount of the resist material and baking the semiconductor structure to form a next resist layer portion of the resist layer. The method additionally includes depositing a conductive material in an opening formed in the resist layer and forming a conductive structure from the conductive material. An interconnect structure is also provided.

Abstract translation: 制造互连结构的方法包括提供半导体结构并执行第一旋转抗蚀剂和烘烤循环。 第一旋转抗蚀剂和烘烤循环包括在半导体结构的一个或多个部分上施加第一预定量的抗蚀剂材料并烘烤半导体结构以形成抗蚀剂层的第一抗蚀剂层部分。 该方法还包括执行下一个旋转抗蚀剂和烘烤循环。 接下来的旋涂抗蚀剂和烘烤循环包括施加下一个预定量的抗蚀剂材料并烘烤半导体结构以形成抗蚀剂层的下一个抗蚀剂层部分。 该方法另外包括在形成于抗蚀剂层中的开口中沉积导电材料并且由导电材料形成导电结构。 还提供互连结构。