公开(公告)号：WO2014004764A1

公开(公告)日：2014-01-03

申请号：PCT/US2013/048067

申请日：2013-06-27

Applicant: POWER INTEGRATIONS, INC.

Inventor： KUDYMOV, Alexey

IPC: H01L29/778 ,  H01L29/40

CPC classification number: H01L23/60 ,  H01L21/8252 ,  H01L27/0274 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/404 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H03K17/08104

Abstract: A semiconductor device includes a substrate and a first active layer disposed over the substrate. The semiconductor device also includes a second active layer disposed on the first active layer such that a lateral conductive channel arises between the first active layer and the second active layer, a source, gate and drain contact are disposed over the second active layer. A conductive charge distribution structure is disposed over the second active layer between the gate and drain contacts. The conductive charge distribution structure is capacitively coupled to the gate contact.

Abstract translation: 半导体器件包括衬底和设置在衬底上的第一有源层。 半导体器件还包括设置在第一有源层上的第二有源层，使得在第一有源层和第二有源层之间产生横向导电沟道，源极，栅极和漏极接触设置在第二有源层上方。 导电电荷分布结构设置在栅极和漏极触点之间的第二有源层上。 导电电荷分布结构电容耦合到栅极接触。

公开(公告)号：WO2022051173A1

公开(公告)日：2022-03-10

申请号：PCT/US2021/047836

申请日：2021-08-27

Applicant: POWER INTEGRATIONS, INC.

Inventor： YANG, Kuo-Chang Robert ,  KUDYMOV, Alexey ,  VARADARAJAN, Kamal Raj ,  ANKOUDINOV, Alexei ,  GEORGESCU, Sorin S.

IPC: H01L29/20 ,  H01L29/40 ,  H01L29/778

Abstract: A die seal ring including a two-dimensional electron gas is presented herein. A semiconductor device comprises an active device region. The active device region comprises a device terminal; and a die seal ring comprising a two dimensional electron gas region surrounds the active device region. By electrically coupling the device terminal to the two dimensional electron gas region, voltages at the semiconductor sidewall may be controlled to substantially equal that of the device terminal.

公开(公告)号：WO2021011163A1

公开(公告)日：2021-01-21

申请号：PCT/US2020/039344

申请日：2020-06-24

Applicant: POWER INTEGRATIONS, INC.

Inventor： YANG, Kuo-Chang ,  GEORGESCU, Sorin ,  KUDYMOV, Alexey ,  VARADARAJAN, Kamal

IPC: H01L29/20 ,  H01L23/64 ,  H01L27/06 ,  H01L29/40 ,  H01L29/778

Abstract: Capacitance networks for enhancing high voltage operation of high electron mobility transistors (HEMTs) are presented herein. A capacitance network, integrated and/or external, may be provided with a fixed number of capacitively coupled field plates to distribute the electric field in the drift region. The capacitively coupled field plates may advantageously be fabricated on the same metal layer to lower cost; and the capacitance network may be provided to control field plate potentials. The potentials on each field plate may be pre-determined through the capacitance network, resulting in a uniform, and/or a substantially uniform electric field distribution along the drift region.

公开(公告)号：WO2017176287A1

公开(公告)日：2017-10-12

申请号：PCT/US2016/026708

申请日：2016-04-08

Applicant: POWER INTEGRATIONS, INC.

Inventor： KUDYMOV, Alexey ,  RAMDANI, Jamal

IPC: H01L21/82 ,  H01L27/02 ,  H01L29/737

Abstract: A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.

Abstract translation: 异质结构半导体器件包括第一有源区和第二有源区，每个有源区彼此电隔离，并且每个有源区包括第一有源层和第二有源层，其间设置有电荷。 功率晶体管形成在第一有源区域中，并且集成栅极电阻器形成在第二有源区域中。 门阵列在功率晶体管的第一有源区上横向延伸。 第一和第二欧姆接触分别设置在集成栅极电阻的第一和第二横向端处，第一和第二欧姆接触电连接到第二有源层的第二部分，第二欧姆接触也电连接到栅极 阵列。 栅极总线电连接到第一欧姆接触。