公开(公告)号：WO2022076199A1

公开(公告)日：2022-04-14

申请号：PCT/US2021/052376

申请日：2021-09-28

Applicant: POWER INTEGRATIONS, INC.

Inventor： YANG, Kuo-Chang Robert ,  GEORGESCU, Sorin S.

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/16 ,  H01L29/20 ,  H03K17/687

Abstract: A lateral surface gate vertical field effect transistor with adjustable output capacitance is described herein. The lateral surface gate vertical field effect transistor includes both a lateral gate and a trench gate. The lateral gate modulates a surface channel and the trench gate includes a controllable depth. The controllable depth may be varied to advantageously adjust output capacitance.

公开(公告)号：WO2022051173A1

公开(公告)日：2022-03-10

申请号：PCT/US2021/047836

申请日：2021-08-27

Applicant: POWER INTEGRATIONS, INC.

Inventor： YANG, Kuo-Chang Robert ,  KUDYMOV, Alexey ,  VARADARAJAN, Kamal Raj ,  ANKOUDINOV, Alexei ,  GEORGESCU, Sorin S.

IPC: H01L29/20 ,  H01L29/40 ,  H01L29/778

Abstract: A die seal ring including a two-dimensional electron gas is presented herein. A semiconductor device comprises an active device region. The active device region comprises a device terminal; and a die seal ring comprising a two dimensional electron gas region surrounds the active device region. By electrically coupling the device terminal to the two dimensional electron gas region, voltages at the semiconductor sidewall may be controlled to substantially equal that of the device terminal.

公开(公告)号：WO2021257303A1

公开(公告)日：2021-12-23

申请号：PCT/US2021/036138

申请日：2021-06-07

Applicant: POWER INTEGRATIONS, INC.

Inventor： VARADARAJAN, Kamal Raj ,  YANG, Kuo-Chang Robert ,  GEORGESCU, Sorin S.

IPC: H01L27/085 ,  H01L27/098 ,  H01L21/82 ,  H01L29/78 ,  H01L29/808 ,  H01L21/8213 ,  H01L29/1608 ,  H01L29/7803 ,  H01L29/8083

Abstract: Auxiliary junction field effect transistors (JFETs) for vertical power devices are disclosed herein. By adjusting a JFET channel width (W2) and providing an auxiliary connection (i.e., a tap connection 154) to one or more unit cells (152) in a power device (e.g., power MOSFET), an auxiliary JFET is formed to function as a tap element. The auxiliary JFET may be advantageously implemented in a conventional silicon (Si) and/or silicon carbide (SiC) process flow without introducing additional process steps. Additionally, the auxiliary JFET (i.e., tap element) may occupy a small portion (e.g., a standard pad size portion) of the total chip area.

公开(公告)号：WO2021202228A1

公开(公告)日：2021-10-07

申请号：PCT/US2021/024090

申请日：2021-03-25

Applicant: POWER INTEGRATIONS, INC.

Inventor： YANG, Kuo-Chang Robert ,  VARADARAJAN, Kamal Raj ,  GEORGESCU, Sorin S.

IPC: H01L29/808 ,  H01L29/78 ,  H01L29/10 ,  H01L29/16 ,  H01L29/06 ,  H01L29/0619 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/7832 ,  H01L29/8083

Abstract: Silicon carbide (SiC) junction field effect transistors (JFETs) are presented herein. A deep implant (e.g., a deep p-type implant) forms a JFET gate (106). JFET gate and JFET source (108) may be implemented with heavily doped n-type (N+) and heavily doped p-type (P+) implants, respectively. Termination regions may be implemented by using equipotential rings formed by deep implants (e.g., deep p-type implants).