公开(公告)号：WO2022271417A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/031542

申请日：2022-05-31

Applicant: WOLFSPEED, INC.

Inventor： MCNUTT, Ty Richard

IPC: H01L29/78 ,  H01L23/367 ,  H01L23/36 ,  H01L24/49 ,  H01L25/072 ,  H01L29/0684 ,  H01L29/1608 ,  H01L29/7811

Abstract: A power semiconductor die includes a substrate and a drift layer on the substrate. The drift layer includes an active area, an edge termination area surrounding the active area, and a thermal dissipation area surrounding the edge termination area. The thermal dissipation area is configured to reduce a thermal resistance of the power semiconductor die. By providing the thermal dissipation area, the operating voltage and/or current of the power semiconductor die can be increased without an increase in the active area. Further, the manufacturing yield of the power semiconductor die can be improved.

公开(公告)号：WO2022136278A2

公开(公告)日：2022-06-30

申请号：PCT/EP2021/086803

申请日：2021-12-20

Applicant: HITACHI ENERGY SWITZERLAND AG

Inventor： WIRTHS, Stephan ,  KNOLL, Lars ,  MIHAILA, Andrei

IPC: H01L29/78 ,  H01L29/16 ,  H01L21/336 ,  H01L29/08 ,  H01L29/423 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1608 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/7828

Abstract: A power semiconductor device (1) is described comprising: - a first main electrode (3), - a second main electrode (4), - a gate electrode layer (5) between the first main electrode (3) and the second main electrode (4), - a semiconductor layer stack (2) between and in electrical contact with the first main electrode (3) and the second main electrode (4), the semiconductor layer stack (2) comprising: - differently doped semiconductor layers, wherein at least two semiconductor layers differ in at least one of their conductivity type and their doping concentration, - a plurality of pillar-shaped or fin-shaped regions (20), which run through the gate electrode layer (5) and which each comprise a contact layer (21) arranged at the first main electrode (3) with a first doping concentration and with a first conductivity type, wherein each contact layer (21) extends to a side (5A) of the gate electrode layer (5) facing the first main electrode (3), the contact layers (21) of adjacent pillar-shaped or fin-shaped regions (20, 930) merge on the side of the gate electrode layer (5, 94) facing the first main electrode (3, 921) so that the contact layers (21) of adjacent pillar-shaped or fin-shaped regions (20, 930) are arranged continuously on the side of the gate electrode layer (5, 94) facing the first main electrode (3, 921).

公开(公告)号：WO2022002111A1

公开(公告)日：2022-01-06

申请号：PCT/CN2021/103440

申请日：2021-06-30

Applicant: XIAMEN SANAN INTEGRATED CIRCUIT CO., LTD.

Inventor： TAO, Yonghong ,  LIN, Zhidong ,  PENG, Zhigao

IPC: H01L29/872 ,  H01L29/868 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/6606

Abstract: A silicon carbide power diode device has a silicon carbide substrate on which a silicon carbide epitaxial layer with an active region is provided. A Schottky metal layer is on the active region, and a first electrode layer is on the Schottky metal layer. A first ohmic contact is on the silicon carbide substrate, and a second electrode layer is on the first ohmic contact. The active region of the silicon carbide epitaxial layer has a plurality of first P-type regions, a plurality of second P-type regions, and N-type regions. The first P-type regions and the second P-type regions lacking an ohmic contact are spaced apart with dimensions of the second P-type regions being minimized and the N-type regions being maximized for given dimensions of the first P-type region. Second ohmic contacts are located between the first P-type region and the Schottky metal layer.

公开(公告)号：WO2021146270A2

公开(公告)日：2021-07-22

申请号：PCT/US2021/013217

申请日：2021-01-13

Applicant: KEMET ELECTRONICS CORPORATION

Inventor： BULTITUDE, John ,  BLAIS, Peter, Alexandre ,  BURK, James, A. ,  MILLER, Galen, W. ,  HAYES, Hunter ,  TEMPLETON, Allen ,  JONES, Lonnie, G. ,  LAPS, Mark, R.

IPC: H01L23/495 ,  H05K1/11 ,  H05K3/46 ,  H01G4/30 ,  H01G4/224 ,  H01G4/228 ,  H01G4/38 ,  H01L25/072 ,  H01L29/1608 ,  H01L29/2003 ,  H05K1/0272 ,  H05K1/145 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/10166 ,  H05K2201/10545 ,  H05K3/328

Abstract: Provided is a high-density multi-component package comprising a first module interconnect pad and a second module interconnect pad. At least two electronic components are mounted to and between the first module interconnect pad and the second module interconnect pad wherein a first electronic component is vertically oriented relative to the first module interconnect pad. A second electronic component is vertically oriented relative to the second module interconnect pad.

公开(公告)号：WO2021145907A1

公开(公告)日：2021-07-22

申请号：PCT/US2020/021542

申请日：2020-03-06

Applicant: MICROCHIP TECHNOLOGY INC.

Inventor： GENDRON-HANSEN, Amaury ,  ODEKIRK, Bruce

IPC: H01L21/265 ,  H01L21/329 ,  H01L21/336 ,  H01L29/872 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02274 ,  H01L21/02293 ,  H01L21/02378 ,  H01L21/02579 ,  H01L21/046 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/67075 ,  H01L27/0927 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802

Abstract: A method for fabricating a silicon carbide semiconductor device includes providing a SiC epitaxial layer disposed over a surface of a SiC substrate, forming an implant aperture in a hardmask layer on a surface of the expitaxial SiC layer, implanting contact and well regions in the SiC epitaxial layer through the hardmask layer, the contact region lying completely within and recessed from edges of the well region by performing one of implanting the well region through the implant aperture, reducing the area of the implant aperture forming a reduced-area contact implant aperture and implanting the contact region through the reduced-area implant aperture to form a contact region, and implanting the contact region through the implant aperture, increasing the area of the implant aperture to form a increased-area well implant aperture and implanting the well region through the increased-area implant aperture to form a well region completely surrounding the contact region.

公开(公告)号：WO2022020147A2

公开(公告)日：2022-01-27

申请号：PCT/US2021/041532

申请日：2021-07-14

Applicant: WOLFSPEED, INC.

Inventor： LICHTENWALNER, Daniel, Jenner ,  RYU, Sei-Hyung ,  HAN, Kijeong ,  VAN BRUNT, Edward, Robert

IPC: H01L29/08 ,  H01L29/16 ,  H01L29/78 ,  H01L29/861 ,  H01L29/872 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/7802

Abstract: A vertical semiconductor device includes one or more of a substrate, a buffer layer over the substrate, one or more drift layers over the buffer layer, and a spreading layer over the one or more drift layers.

公开(公告)号：WO2021257634A1

公开(公告)日：2021-12-23

申请号：PCT/US2021/037522

申请日：2021-06-15

Applicant: WOLFSPEED, INC.

Inventor： LICHTENWALNER, Daniel, Jenner ,  ISLAM, Naeem

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

Abstract: A vertical field effect device having a body, gate dielectric, and a gate electrode, which is in a trench that extends into the body from the top surface of the body and is located between first and second source regions. The first and second regions vertically overlap the gate electrode. The first and second channel regions laterally overlap a bottom of the gate electrode, such that each channel formed in the first and second source regions have a horizontal segment where the first and second channel regions laterally overlap the bottom of the gate electrode. In another embodiment, the first and second channel regions also vertically overlap the gate electrode such that each channel formed in the first and second source regions also have a vertical segment where the first and second channel regions vertically overlap the gate electrode.

公开(公告)号：WO2021257180A1

公开(公告)日：2021-12-23

申请号：PCT/US2021/028740

申请日：2021-04-23

Applicant: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.

Inventor： SOM, Shamit ,  ATHERTON, John Stephen ,  STRUBLE, Wayne Mack ,  BARRETT, Jason Matthew ,  YAMUJALA, Nishant R.

IPC: H01L21/8234 ,  H01L23/48 ,  H01L23/528 ,  H01L27/02 ,  H01L27/085 ,  H01L29/417 ,  H03F1/02 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/20 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/0605 ,  H01L27/0617 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/778 ,  H03F1/0288 ,  H03F2200/451 ,  H03F3/195

Abstract: Integrated semiconductor devices are described. In one example, an integrated device includes first and second transistors formed on a substrate, where the transistors share a terminal metal feature (220) to reduce a size of the integrated device. The terminal metal feature can include a shared source electrode metalization, for example, although other electrode metalizations can be shared. In other aspects, a first width of a gate of the first transistor can be greater than a second width of a gate of the second transistor, and the shared metalization can taper from the first width to the second width. The integrated device can also include a metal ground plane on a backside of the substrate, and the terminal metal feature can also include an in-source via for the shared source electrode metalization. The in-source via can electrically couple the shared source electrode metalization to the metal ground plane.

公开(公告)号：WO2021247147A1

公开(公告)日：2021-12-09

申请号：PCT/US2021/027259

申请日：2021-04-14

Applicant: CREE, INC.

Inventor： STEINMANN, Philipp ,  VAN BRUNT, Edward ,  PARK, Jae Hyung ,  DASIKA, Vaishno

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/336 ,  H01L29/086 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7833

Abstract: A semiconductor device includes a semiconductor layer structure comprising a source/drain region, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer. The source/drain region comprises a first portion comprising a first dopant concentration and a second portion comprising a second dopant concentration. The second portion is closer to a center of the gate electrode than the first portion.

公开(公告)号：WO2021202075A1

公开(公告)日：2021-10-07

申请号：PCT/US2021/021848

申请日：2021-03-11

Applicant: CREE, INC.

Inventor： NOORI, Basim ,  MARBELL, Marvin ,  LIM, Kwangmo Chris ,  MU, Qianli

IPC: H01L23/66 ,  H01L23/538 ,  H01L25/07 ,  H01L23/31 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2223/6683 ,  H01L2224/06181 ,  H01L23/3677 ,  H01L23/49503 ,  H01L23/49531 ,  H01L23/49548 ,  H01L23/49589 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/18 ,  H01L25/0657 ,  H01L25/072 ,  H01L29/1608 ,  H01L29/2003 ,  H01L2924/19107 ,  H03F3/193 ,  H03F3/195 ,  H03F3/213

Abstract: An integrated circuit device package includes a substrate, a first die comprising active electronic components attached to the substrate, and package leads configured to conduct electrical signals between the first die and an external device. At least one integrated interconnect structure is provided on the first die opposite the substrate. The at least one integrated interconnect structure extends from the first die to an adjacent die attached to the substrate and/or to at least one of the package leads, and provides electrical connection therebetween. Related devices and power amplifier circuits are also discussed.