公开(公告)号：WO2012027424A1

公开(公告)日：2012-03-01

申请号：PCT/US2011/048887

申请日：2011-08-24

Applicant: QUALCOMM INCORPORATED ,  RAMADOSS, Vivek ,  JHA, Gopal C. ,  HEALY, Christopher J.

Inventor： RAMADOSS, Vivek ,  JHA, Gopal C. ,  HEALY, Christopher J.

IPC: H01L23/13 ,  H01L23/498 ,  H01L23/552

CPC classification number: H01L23/49822 ,  H01L23/13 ,  H01L23/552 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: A hybrid multilayer substrate in an electronic package. The substrate includes a first portion having m layers and a second portion having n layers such that m is less than n. The first portion has a first height and the second portion has a second height. The first height is different than the second height. In another embodiment, a surface is formed between the first portion and the second portion, and a shielding material can be applied to the surface. In a different embodiment, the hybrid multilayer substrate is manufactured for shielding a first die from a second die.

Abstract translation: 电子封装中的混合多层基板。 衬底包括具有m层的第一部分和具有n层的第二部分，使得m小于n。 第一部分具有第一高度，第二部分具有第二高度。 第一高度与第二高度不同。 在另一个实施例中，在第一部分和第二部分之间形成表面，并且可以将屏蔽材料施加到表面。 在不同的实施例中，制造用于将第一管芯与第二管芯屏蔽的混合多层基板。

公开(公告)号：WO2014110482A1

公开(公告)日：2014-07-17

申请号：PCT/US2014/011230

申请日：2014-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： HEALY, Christopher J. ,  JHA, Gopal C. ,  ALDRETE, Manuel

IPC: H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H01L21/56

CPC classification number: H05K1/0271 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/49816 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10145 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/12042 ,  H01L2924/3841 ,  H05K3/4038 ,  H05K2201/0305 ,  Y10T29/49165 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Improved Molded Laser Package (MLP) Packages which include a relief path for pressure and reduces the risk of shorting adjacent solder balls are provided. The MLP packages may include a gutter integrally connected to one or more through mold vias allowing a path to relieve pressure created when moisture gets entrapped in through mold vias, during the manufacturing process, while also reducing the risk of solder shorts between adjacent solder balls located in the through mold vias. Additionally, MLP packages which include gutters integrally connected to one or more through mold vias may enable tighter bump pitch and thinner packages. As a result, process margins and risks associated with surface mount technology (SMT) may be improved and provide more flexibility on inventory staging.

Abstract translation: 改进的模制激光封装（MLP）提供了包括压力释放路径和降低相邻焊球短路风险的封装。 MLP包装可以包括一个整体地连接到一个或多个通过模具通孔的沟槽，允许在制造过程期间通过模具通道将水分截留时产生的压力减小的路径，同时还降低相邻焊球之间的焊料短路的风险 在通孔中通孔。 此外，包括整体连接到一个或多个通过模具通孔的沟槽的MLP封装可以实现更紧密的突起间距和更薄的封装。 因此，可能会提高与表面贴装技术（SMT）相关的工艺余量和风险，并为库存阶段提供更大的灵活性。

公开(公告)号：WO2012037263A1

公开(公告)日：2012-03-22

申请号：PCT/US2011/051612

申请日：2011-09-14

Applicant: QUALCOMM INCORPORATED ,  RAMADOSS, Vivek ,  JHA, Gopal C. ,  HEALY, Christopher J.

Inventor： RAMADOSS, Vivek ,  JHA, Gopal C. ,  HEALY, Christopher J.

IPC: H01L23/367 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/562 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic package with improved warpage compensation. The electronic package includes a mold cap having a variable thickness. The variable thickness can have a mound or dimple design. In another embodiment, a method is provided for reducing unit warpage of an electronic package by designing the topography of a mold cap to compensate for warpage.

Abstract translation: 具有改善翘曲补偿的电子封装。 电子封装包括具有可变厚度的模具盖。 可变厚度可以具有土墩或凹坑设计。 在另一个实施例中，提供了一种用于通过设计模具盖的形貌以减少翘曲来减小电子封装的单元翘曲的方法。