公开(公告)号：WO2010108032A1

公开(公告)日：2010-09-23

申请号：PCT/US2010/027859

申请日：2010-03-18

Applicant: QUALCOMM INCORPORATED ,  SEO, Dongwon ,  WADHWA, Sameer

Inventor： SEO, Dongwon ,  WADHWA, Sameer

IPC: H03L1/00 ,  H03K3/011 ,  H03K3/03

CPC classification number: H03L1/00 ,  H03K3/0322

Abstract: An integrated circuit incorporating a bias circuit for a current-controlled oscillator (ICO) with improved power supply rejection ratio (PSRR) is described. The bias circuit for the ICO includes two error amplifiers. The first error amplifier regulates the bias voltage, VBN, referenced to a ground supply (GND). The second error amplifier regulates the bias voltage, VBP, referenced to a positive power supply (VDD). The VBP and VBN bias voltages have improved PSRR relative to conventional ICO bias circuits for noise injected into VDD and GND.

Abstract translation: 描述了具有改善的电源抑制比（PSRR）的电流控制振荡器（ICO）的偏置电路的集成电路。 ICO的偏置电路包括两个误差放大器。 第一个误差放大器调节参考接地电源（GND）的偏置电压VBN。 第二个误差放大器调节参考正电源（VDD）的偏置电压VBP。 相对于常规ICO偏置电路，VBP和VBN偏置电压对于注入VDD和GND的噪声具有改进的PSRR。

公开(公告)号：WO2008157295A1

公开(公告)日：2008-12-24

申请号：PCT/US2008/066839

申请日：2008-06-13

Applicant: QUALCOMM Incorporated ,  SEO, Dongwon ,  SUN, Bo ,  SAHOTA, Gurkanwal Singh (Kamal) ,  MISHRA, Manu

Inventor： SEO, Dongwon ,  SUN, Bo ,  SAHOTA, Gurkanwal Singh (Kamal) ,  MISHRA, Manu

IPC: H03M1/00

CPC classification number: H03M1/002 ,  H03M1/682 ,  H03M1/747

Abstract: A digital-to-analog converter, RF transmit channel and method, for converting a digital signal of N bits having a set M of most significant bits and a set L of least significant bits to an analog signal, are disclosed. The digital signal defines a set of coded values which are converted to analog values and modulated on to a RF signal. The digital-to-analog converter includes a plurality of switches and an output stage, for providing at least a first differential output signal and a second differential output signal. The output stage modifies currents received from the plurality of switches, such that the value of the average output current of the first and second differential outputs signals is steered to a relatively low current value at the mid-point of the coded values.

Abstract translation: 公开了用于将具有最高有效位的集合M的N位的数字信号和最低有效位的集合L转换为模拟信号的数模转换器，RF发送信道和方法。 数字信号定义了一组编码值，它们被转换为模拟值并被调制到RF信号上。 数模转换器包括多个开关和输出级，用于至少提供第一差分输出信号和第二差分输出信号。 输出级修改从多个开关接收的电流，使得第一和第二差分输出信号的平均输出电流的值被转向在编码值的中点处的相对低的电流值。

公开(公告)号：WO2011041612A1

公开(公告)日：2011-04-07

申请号：PCT/US2010/051007

申请日：2010-09-30

Applicant: QUALCOMM INCORPORATED ,  SEO, Dongwon ,  SARIPALLI, Ganesh ,  SONG, Tongyu ,  TALEIE, Shahin, Mehdizad ,  KONG, Derui

Inventor： SEO, Dongwon ,  SARIPALLI, Ganesh ,  SONG, Tongyu ,  TALEIE, Shahin, Mehdizad ,  KONG, Derui

IPC: H03M1/74

CPC classification number: H03M1/742 ,  H03F1/223 ,  H03F1/3241 ,  H03F3/195 ,  H03F3/245 ,  H03F3/45183

Abstract: A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.

Abstract translation: 描述用于数模转换的电路。 该电路包括一个数模转换器（DAC）。 DAC包括双级联电流源和差分电流模式开关（DCMS）。 电路还包括直流（DC）偏置级。 该电路还包括负载衰减器。 双级联电流源可以在DCMS和导轨电压之间。

公开(公告)号：WO2008137752A1

公开(公告)日：2008-11-13

申请号：PCT/US2008/062515

申请日：2008-05-02

Applicant: QUALCOMM Incorporated ,  DABAG, Hayg-Taniel ,  MCALLISTER, Gene, H. ,  SEO, Dongwon

Inventor： DABAG, Hayg-Taniel ,  MCALLISTER, Gene, H. ,  SEO, Dongwon

IPC: H03M1/06 ,  H03M1/74

CPC classification number: H03M1/0665 ,  H03M1/0673 ,  H03M1/74 ,  H03M3/502

Abstract: Techniques for dynamically selecting circuit elements to combat mismatches are described. In one design, an apparatus includes first, second, and third circuits. The first circuit receives input data and provides first signals that are asserted based on the input data, e.g., with thermometer decoding. The second circuit receives the first signals and provides second signals used to select circuit elements, e.g., current sources, capacitors, resistors, etc. The third circuit generates a control for the second circuit, and the second circuit maps the first signals to the second signals based on this control. In one design, the second circuit includes a set of multiplexers and a control circuit. The multiplexers provides the first signals, circularly rotated by an amount determined by the control, as the second signals. The control circuit accumulates control data (e.g., the input data, pseudo-random data, or a fixed value) with the current control value to obtain new control value.

Abstract translation: 描述了用于动态选择电路元件以抵抗不匹配的技术。 在一种设计中，装置包括第一，第二和第三电路。 第一电路接收输入数据并提供基于输入数据而被确定的第一信号，例如用温度计解码。 第二电路接收第一信号并提供用于选择电路元件的第二信号，例如电流源，电容器，电阻器等。第三电路产生用于第二电路的控制，第二电路将第一信号映射到第二信号 基于此控制的信号。 在一种设计中，第二电路包括一组多路复用器和一个控制电路。 复用器提供循环旋转了由控制确定的量的第一信号作为第二信号。 控制电路用当前控制值累积控制数据（例如，输入数据，伪随机数据或固定值）以获得新的控制值。

公开(公告)号：WO2006036900A1

公开(公告)日：2006-04-06

申请号：PCT/US2005/034441

申请日：2005-09-22

Applicant: QUALCOMM INCORPORATED ,  SEO, Dongwon

Inventor： SEO, Dongwon

IPC: H03M1/06 ,  H03F1/32

CPC classification number: H03K17/04106 ,  H03M1/745

Abstract: A high-speed, high-accuracy DAC has multiple current switches. Each current switch includes a current source that provides a reference current, first and second circuit elements that couple to the current source, and first and second transistors that couple to the first and second circuit elements, respectively. The first transistor provides the reference current to a first output when enabled, and the second transistor provides the reference current to a second output when enabled. The first and second circuit elements provide source degeneration for the first and second transistors, extend the linear operating region for these transistors, and may be implemented with either transistors that are always turned on or resistors. The first and second transistors and the first and second circuit elements may be P-channel field effect transistors (P-FETs), N-channel field effect transistors (N-FETs), or transistors of some other type.

Abstract translation: 高速，高精度DAC具有多个电流开关。 每个电流开关包括提供耦合到电流源的参考电流，第一和第二电路元件以及耦合到第一和第二电路元件的第一和第二晶体管的电流源。 当使能时，第一晶体管将参考电流提供给第一输出，并且当使能时，第二晶体管将参考电流提供给第二输出。 第一和第二电路元件为第一和第二晶体管提供源极退化，扩展这些晶体管的线性工作区域，并且可以通过总是导通的晶体管或电阻来实现。 第一和第二晶体管以及第一和第二电路元件可以是P沟道场效应晶体管（P-FET），N沟道场效应晶体管（N-FET）或其他类型的晶体管。

公开(公告)号：WO2013044263A2

公开(公告)日：2013-03-28

申请号：PCT/US2012/056963

申请日：2012-09-24

Applicant: QUALCOMM INCORPORATED ,  CHIABURU, Liviu ,  TALEIE, Shahin Mehdizah ,  SEO, Dongwon ,  SILVERSTEIN, Roy B.

Inventor： CHIABURU, Liviu ,  TALEIE, Shahin Mehdizah ,  SEO, Dongwon ,  SILVERSTEIN, Roy B.

IPC: H04L25/02

CPC classification number: H04L25/0278

Abstract: A buffer amplifier has a power on state and a sleep state. During regular operation a coupling state of a load to an output node is detected using feedback voltage. In a sleep mode and in a power collapse mode a detection current is injected into the output node, to produce a voltage, and the coupling state of the load is detected from the voltage. Optionally, the detection current and detecting of the voltage on the output node is enables by a low duty cycle clock. Optionally, signals generated in detecting the coupling state are qualified through a debounce circuit.

Abstract translation: 缓冲放大器具有通电状态和睡眠状态。 在正常操作期间，使用反馈电压来检测负载到输出节点的耦合状态。 在睡眠模式和功率崩溃模式中，检测电流被注入到输出节点中以产生电压，并且从电压检测负载的耦合状态。 可选地，通过低占空比时钟启用检测电流和输出节点上的电压检测。 可选地，通过去抖动电路来限定在检测耦合状态时产生的信号。

公开(公告)号：WO2009151670A2

公开(公告)日：2009-12-17

申请号：PCT/US2009/036444

申请日：2009-03-08

Applicant: QUALCOMM INCORPORATED ,  SEO, Dongwon ,  McALLISTER, Gene H. ,  DABAG, Hayg-Taniel

Inventor： SEO, Dongwon ,  McALLISTER, Gene H. ,  DABAG, Hayg-Taniel

IPC: G06G7/18 ,  H03M1/66 ,  H03M1/00

CPC classification number: H03M1/004 ,  H03M1/066 ,  H03M1/0665 ,  H03M1/0673 ,  H03M1/74 ,  H03M3/502

Abstract: According to at least one embodiment of the invention, an apparatus may include first, second and third circuits. The first circuit receives input data and provides a plurality of first signals asserted based on the input data. The second circuit receives the plurality of first signals and provides a plurality of second signals used to select a plurality of circuit elements. The third circuit generates a control for the second circuit using a fractional data weight of the input data, the second circuit mapping the plurality of first signals to the plurality of second signals based on the control from the third circuit.

Abstract translation: 根据本发明的至少一个实施例，装置可以包括第一，第二和第三电路。 第一电路接收输入数据并提供基于输入数据而断言的多个第一信号。 第二电路接收多个第一信号并提供用于选择多个电路元件的多个第二信号。 第三电路使用输入数据的分数数据权重生成第二电路的控制，第二电路基于来自第三电路的控制将多个第一信号映射到多个第二信号。

公开(公告)号：WO2009026469A1

公开(公告)日：2009-02-26

申请号：PCT/US2008/073928

申请日：2008-08-21

Applicant: QUALCOMM INCORPORATED ,  DABAG, Hayg ,  SEO, Dongwon ,  MISHRA, Manu

Inventor： DABAG, Hayg ,  SEO, Dongwon ,  MISHRA, Manu

IPC: H03F3/30 ,  H03F3/45 ,  H03F1/52

CPC classification number: H03F3/45192 ,  H03F1/52 ,  H03F1/523 ,  H03F3/303 ,  H03F2203/30015 ,  H03F2203/30084 ,  H03F2203/30117 ,  H03F2203/45244 ,  H03F2203/45626 ,  H03F2203/45732

Abstract: An output stage (123) includes two transistors (T3, T4) (switching transistor, and biasing transistor) coupled in series in a pullup current path between a VDDA node and an output node, (120) and also includes two transistors (Tl, T2) (switching transistor and biasing transistor) coupled in series in a pulldown current path between the output node (121) and a ground node. Providing the biasing transistors (T2,T4) reduces the maximum voltage dropped across the transistors, thereby allowing the transistors to have lower breakdown voltages than VDDA. An adaptive biasing circuit (26) adjusts the gate voltage on a biasing transistor (T2,T4) based on the output node (121) voltage. If the output voltage is in a midrange, then the gate voltage is set farther away from a rail voltage in order to reduce voltage stress. If the output voltage is in a range closer to the rail voltage, then the gate voltage is set closer to the rail voltage, thereby facilitating rail-to-rail output voltage swings.

Abstract translation: 输出级（123）包括串联耦合在VDDA节点和输出节点之间的上拉电流路径（120）中的两个晶体管（T3，T4）（开关晶体管和偏置晶体管），并且还包括两个晶体管（T1， T2）（开关晶体管和偏置晶体管），其串联耦合在输出节点（121）和接地节点之间的下拉电流路径中。 提供偏置晶体管（T2，T4）降低了跨越晶体管的最大电压，从而允许晶体管具有比VDDA更低的击穿电压。 自适应偏置电路（26）基于输出节点（121）电压来调节偏置晶体管（T2，T4）上的栅极电压。 如果输出电压处于中频范围，则栅极电压被设置得更远离轨道电压，以便减小电压应力。 如果输出电压在更接近导轨电压的范围内，则栅极电压被设置为更接近导轨电压，从而便于轨至轨输出电压摆动。

公开(公告)号：WO2008002041A1

公开(公告)日：2008-01-03

申请号：PCT/KR2007/003064

申请日：2007-06-25

Applicant: SEO, Dongwon

Inventor： SEO, Dongwon

IPC: A47K10/16

CPC classification number: B65D25/082 ,  B65D25/087 ,  B65D75/326

Abstract: A packaging case for disposable compressed tissues is provided, which includes: a first accommodation portion which accommodates liquid; a second accommodation portion which has a stepped portion on the upper portion of the first accommodation portion so that the cross- sectional area of the second accommodation portion is larger than that of the first accommodation portion, and is partitioned from the first accommodation portion by a separable film which is thermally fused on the stepped portion by a thermal fusion operation, to thus ac¬ commodate tissues which have been compressed and dried; and a cover film which covers the upper portion of the second accommodation portion, wherein a bursting strength of the cover film is larger than that of the separable film when pressurized, so that the separable film is bursted before the cover film is bursted when pressurized.

Abstract translation: 提供一次性压缩组织的包装盒，其包括：容纳液体的第一容纳部分; 第二容纳部，其在所述第一容纳部的上部具有阶梯部，使得所述第二容纳部的横截面积大于所述第一容纳部的横截面积，并且与所述第一容纳部分隔开一个 通过热熔融操作在台阶部分热熔融的可分离膜，从而使经过压缩和干燥的组织得以充分; 以及覆盖所述第二容纳部的上部的覆盖膜，其中，当加压时，所述覆盖膜的破裂强度大于所述可分离膜的破裂强度，使得所述可分离膜在加压时在覆盖膜破裂之前爆裂。

公开(公告)号：WO2017151290A1

公开(公告)日：2017-09-08

申请号：PCT/US2017/017264

申请日：2017-02-09

Applicant: QUALCOMM INCORPORATED

Inventor： SAPUTRA, Nitz ,  LEE, Sang Min ,  SEO, Dongwon

IPC: H03B5/26

CPC classification number: H03B5/26 ,  H03B5/04

Abstract: Circuits and methods for compensating variation in an amplitude-regulated oscillator are provided. In one example, the oscillator includes a diode clamp having back-to-back diode-connected transistors with body terminals. Circuits and methods modulate a body-source voltage of the diode-connected transistors to compensate for process, temperature, and voltage variation.

Abstract translation: 提供了用于补偿幅度调节振荡器中的变化的电路和方法。 在一个示例中，振荡器包括具有与体端子连接的背对背二极管连接的晶体管的二极管钳位。 电路和方法调制二极管连接的晶体管的体源电压以补偿过程，温度和电压变化。