公开(公告)号：WO2010108032A1

公开(公告)日：2010-09-23

申请号：PCT/US2010/027859

申请日：2010-03-18

Applicant: QUALCOMM INCORPORATED ,  SEO, Dongwon ,  WADHWA, Sameer

Inventor： SEO, Dongwon ,  WADHWA, Sameer

IPC: H03L1/00 ,  H03K3/011 ,  H03K3/03

CPC classification number: H03L1/00 ,  H03K3/0322

Abstract: An integrated circuit incorporating a bias circuit for a current-controlled oscillator (ICO) with improved power supply rejection ratio (PSRR) is described. The bias circuit for the ICO includes two error amplifiers. The first error amplifier regulates the bias voltage, VBN, referenced to a ground supply (GND). The second error amplifier regulates the bias voltage, VBP, referenced to a positive power supply (VDD). The VBP and VBN bias voltages have improved PSRR relative to conventional ICO bias circuits for noise injected into VDD and GND.

Abstract translation: 描述了具有改善的电源抑制比（PSRR）的电流控制振荡器（ICO）的偏置电路的集成电路。 ICO的偏置电路包括两个误差放大器。 第一个误差放大器调节参考接地电源（GND）的偏置电压VBN。 第二个误差放大器调节参考正电源（VDD）的偏置电压VBP。 相对于常规ICO偏置电路，VBP和VBN偏置电压对于注入VDD和GND的噪声具有改进的PSRR。

公开(公告)号：WO2013022678A3

公开(公告)日：2013-02-14

申请号：PCT/US2012/049224

申请日：2012-08-01

Applicant: QUALCOMM INCORPORATED ,  RAGHUNATHAN, Ashwin ,  PEDRALI-NOY, Marzio ,  WADHWA, Sameer

Inventor： RAGHUNATHAN, Ashwin ,  PEDRALI-NOY, Marzio ,  WADHWA, Sameer

IPC: H03L7/24 ,  H03L7/07

Abstract: An injection-locked oscillator circuit includes a master oscillator, a slave oscillator, and an injection lock control circuit. The slave oscillator is decoupled from the master oscillator (for example, due to an unlock condition). When the slave is free running, its oscillating frequency is adjusted (for example, as a function of a supply voltage). After an amount of time, the slave is to be relocked to the master (for example, due the unlock condition no longer being present). The slave oscillating frequency is made to be slightly lower than the master oscillating frequency. The slave is then only recoupled to the master upon detection of an opposite-phase condition between the master oscillator output signal and the slave oscillator output signal. By only recoupling the slave to the master during opposite-phase conditions, frequency overshoots in the slave oscillating frequency are avoided that may otherwise occur were the recoupling done during in-phase conditions.

公开(公告)号：WO2010068682A3

公开(公告)日：2010-06-17

申请号：PCT/US2009/067359

申请日：2009-12-09

Applicant: QUALCOMM Incorporated ,  WADHWA, Sameer

Inventor： WADHWA, Sameer

IPC: G05F1/56 ,  G05F1/575

Abstract: A low drop-out (LDO) voltage regulator with a wide bandwidth power supply rejection ratio (PSRR) is described. In one aspect, the LDO voltage regulator includes two individual voltage regulator circuit stages. A first stage voltage regulator circuit output is at an intermediate voltage (VINT) between an input supply voltage (VDD) and a final regulated output voltage (VREG). A second stage voltage regulator circuit output is at the final regulated output voltage (VREG) and is optimized for noise-sensitive analog circuits across a wide operating bandwidth. The first stage voltage regulator circuit has a zero frequency while the second stage voltage regulator circuit has a matching pole frequency to minimize the AC response from VDD to VREG across all frequencies.

公开(公告)号：WO2011050216A2

公开(公告)日：2011-04-28

申请号：PCT/US2010/053629

申请日：2010-10-21

Applicant: QUALCOMM Incorporated ,  WADHWA, Sameer ,  PEDRALI-NOY, Marzio

Inventor： WADHWA, Sameer ,  PEDRALI-NOY, Marzio

IPC: H03K5/156

CPC classification number: H03K5/1565

Abstract: Closed-loop techniques for adjusting the duty cycle of a cyclical signal, e.g., a clock signal, to approach a target value. In an exemplary embodiment, a charge pump is coupled to a charge and sample module, which drives a de-skew circuit in a negative feedback loop. The charge and sample module couples the charge pump to the integration capacitor during two of four successive phases, and also couples the integration capacitor to sampling capacitors during the other two of the four successive phases. The voltages across the sampling capacitors may be used to control the de-skew circuit, which adjusts the duty cycle of a cyclical signal to be adjusted.

Abstract translation: 用于调整循环信号（例如时钟信号）的占空比以接近目标值的闭环技术。 在示例性实施例中，电荷泵耦合到充电和采样模块，其在负反馈回路中驱动去偏斜电路。 充电和采样模块在四个连续阶段中的两个阶段期间将电荷泵耦合到积分电容器，并且还在四个连续阶段中的另外两个阶段期间将积分电容器耦合到采样电容器。 采样电容器两端的电压可用于控制去偏移电路，该电路调整待调整的循环信号的占空比。

公开(公告)号：WO2023004570A1

公开(公告)日：2023-02-02

申请号：PCT/CN2021/108594

申请日：2021-07-27

Applicant: QUALCOMM INCORPORATED ,  WADHWA, Sameer ,  MOHAN, Suren ,  ZHU, Peiyu ,  LI, Ren ,  SRIVASTAVA, Ankit ,  MIRHAJ, Seyed Arash

Inventor： WADHWA, Sameer ,  MOHAN, Suren ,  ZHU, Peiyu ,  LI, Ren ,  SRIVASTAVA, Ankit ,  MIRHAJ, Seyed Arash

IPC: G06N3/04 ,  G06N3/063

Abstract: Certain aspects provide an apparatus for signal processing in a neural network. The apparatus generally includes computation circuitry configured to perform a convolution operation, the computation circuitry having multiple input rows, and an activation buffer having multiple buffer segments coupled to the multiple input rows of the computation circuitry, respectively. In some aspects, each of the multiple buffer segments comprises a first multiplexer having a plurality of multiplexer inputs, and each of the plurality of multiplexer inputs of one of the first multiplexers on one of the multiple buffer segments is coupled to a data output of the activation buffer on another one of the multiple buffer segments.

公开(公告)号：WO2012139078A1

公开(公告)日：2012-10-11

申请号：PCT/US2012/032647

申请日：2012-04-06

Applicant: QUALCOMM INCORPORATED ,  RAGHUNATHAN, Ashwin ,  PEDRALI-NOY, Marzio ,  WADHWA, Sameer

Inventor： RAGHUNATHAN, Ashwin ,  PEDRALI-NOY, Marzio ,  WADHWA, Sameer

IPC: H03L7/099 ,  H03L7/24

CPC classification number: H03L7/0995 ,  H03L7/0805 ,  H03L7/099 ,  H03L7/24

Abstract: A supply-regulated VCO exhibits reduced or no supply sensitivity peaking. The VCO includes an oscillator whose supply current is regulated to control the oscillating frequency of the oscillator. A VCO input signal controls the supply current so that there is a relationship between the input signal and the oscillator output frequency. Power supply noise that might otherwise affect oscillator operation is shunted from a supply current input lead of the oscillator to ground by a bypass capacitor. In one example, an auxiliary circuit supplies an auxiliary supply current to the oscillator, thereby reducing the amount of supply current a supply regulation control loop circuit must supply. In another example, a supply regulation control loop circuit supplies a control current to a main oscillator, but the bypass capacitor is not coupled to this oscillator but rather is coupled to a slave oscillator that is injection locked to the main oscillator.

Abstract translation: 供应调节的VCO表现出减少或没有供应灵敏度峰值。 VCO包括一个振荡器，其供电电流被调节以控制振荡器的振荡频率。 VCO输入信号控制电源电流，使得输入信号和振荡器输出频率之间存在关系。 否则可能会影响振荡器运行的电源噪声从旁路电容器的振荡器的电源电流输入引脚分流到地。 在一个示例中，辅助电路向振荡器提供辅助电源电流，从而减少供电调节控制回路电路必须供应的供电电流量。 在另一示例中，电源调节控制回路电路向主振荡器提供控制电流，但是旁路电容器不耦合到该振荡器，而是耦合到被注入锁定到主振荡器的从属振荡器。

公开(公告)号：WO2011133699A1

公开(公告)日：2011-10-27

申请号：PCT/US2011/033297

申请日：2011-04-20

Applicant: QUALCOMM INCORPORATED ,  RAGHUNATHAN, Ashwin ,  WADHWA, Sameer ,  PEDRALI-NOY, Marzio

Inventor： RAGHUNATHAN, Ashwin ,  WADHWA, Sameer ,  PEDRALI-NOY, Marzio

IPC: H03L7/00

CPC classification number: H03L7/0896

Abstract: A charge pump includes an UP current mirror and a DN current mirror. The UP current mirror is controlled by an input UP signal and supplies charge onto an output node. The DN current mirror is controlled by an input DN signal and draws charge from the output node. The input UP and DN signals may be received from a phase detector in a Phase-Locked Loop (PLL). To prevent disturbances on bias nodes of the UP and DN current mirrors that otherwise might occur, replica circuits of portions of the UP and DN current mirrors are provided. Each replica circuit is coupled to a bias node of a corresponding current mirror, but is controlled by an input signal of opposite polarity to the input signal that controls the current mirror so that the replica circuit creates disturbances that tend to counteract disturbances created by switching of the current mirror.

Abstract translation: 电荷泵包括UP电流镜和DN电流镜。 UP电流镜由输入UP信号控制，并将电荷提供到输出节点上。 DN电流镜由输入DN信号控制，并从输出节点抽取电荷。 可以从锁相环（PLL）中的相位检测器接收输入的UP和DN信号。 为了防止UP和DN电流镜的偏置节点的干扰，否则可能发生，UP和DN电流镜的部分的复制电路被提供。 每个复制电路耦合到相应的电流镜的偏置节点，但是由与控制电流镜的输入信号相反极性的输入信号控制，使得复制电路产生趋向于抵消通过切换产生的干扰而产生的干扰的干扰 当前的镜子。

公开(公告)号：WO2009117428A3

公开(公告)日：2009-09-24

申请号：PCT/US2009/037416

申请日：2009-03-17

Applicant: QUALCOMM MEMS TECHNOLOGIES, INC. ,  WADHWA, Sameer

Inventor： WADHWA, Sameer

IPC: G05F1/565 ,  G02B26/00 ,  G09G3/34

Abstract: Power efficient power supply regulator circuits are disclosed. The circuits are configured to modify their overhead current according to current load. This is particularly advantageous for use in display devices with widely varying current loads. Such displays include bi-stable displays, such as interferometric modulation displays, LCD displays, and DMD displays.

公开(公告)号：WO2008097750A1

公开(公告)日：2008-08-14

申请号：PCT/US2008/052229

申请日：2008-01-28

Applicant: QUALCOMM MEMS TECHNOLOGIES, INC. ,  WADHWA, Sameer ,  ANTONIO, Franklin ,  ANDERSON, Michael, Hugh

Inventor： WADHWA, Sameer ,  ANTONIO, Franklin ,  ANDERSON, Michael, Hugh

IPC: G09G3/34

CPC classification number: G09G3/3466 ,  G02B26/001 ,  G09G3/20 ,  G09G2310/0218 ,  G09G2310/0267

Abstract: A display array which can reduce the row connections between the display and the driver circuit and methods of manufacturing and operating the same are disclosed. In one embodiment, a display device comprises an array of microelectromechanical system (MEMS) display elements (30) and a plurality of passive impedance network circuits (52) coupled to said array and configured to provide row output voltages to drive said array. Each passive impedance network comprises an output to a row of display elements and three or more inputs. No more than one input is shared by two passive impedance networks.

Abstract translation: 公开了可以减少显示器和驱动电路之间的行连接的显示阵列及其制造和操作方法。 在一个实施例中，显示装置包括微机电系统（MEMS）显示元件阵列和耦合到所述阵列的多个被动阻抗网络电路（52），并配置成提供行输出电压来驱动所述阵列。 每个被动阻抗网络包括输出到一行显示元件和三个或更多个输入。 两个无源阻抗网络共享不超过一个输入。

公开(公告)号：WO2006102390A1

公开(公告)日：2006-09-28

申请号：PCT/US2006/010363

申请日：2006-03-22

Applicant: SPANSION LLC ,  WADHWA, Sameer ,  VENKATESH, Bhimachar

Inventor： WADHWA, Sameer ,  VENKATESH, Bhimachar

IPC: G11C16/30 ,  G11C5/14 ,  G11C16/24 ,  G11C7/12

CPC classification number: G11C16/24 ,  G11C7/06 ,  G11C7/067 ,  G11C7/12 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/28 ,  G11C16/30 ,  G11C29/026 ,  G11C2029/1204 ,  G11C2207/063

Abstract: The present invention facilitates more accurate data reads by compensating for parasitic behavior (662) - thus regulating the voltage at the drain (610) of a core memory cell (604) rather than at the output of a sensing circuit. More particularly, respective voltages at one or more nodes (660), such as the start of a bitline at a sensing circuit, for example, are adjusted to compensate for voltage drops that may occur due to parasitic behavior (662). Maintaining the substantially constant voltage levels at core memory cells allows comparisons to be made under ideal conditions while reducing the side leakages in virtual ground schemes. This mitigates margin loss and facilitates more reliable data sensing.

Abstract translation: 本发明通过补偿寄生行为（662）来促进更准确的数据读取，从而调节核心存储器单元（604）的漏极（610）处的电压，而不是在感测电路的输出处。 更具体地，例如调整一个或多个节点（660）处的各个电压（例如感测电路处的位线开始）以补偿由于寄生行为可能发生的电压降（662）。 在核心存储器单元处保持基本恒定的电压电平允许在理想条件下进行比较，同时减少虚拟接地方案中的侧漏。 这减轻了边际损失，并促进了更可靠的数据传感。