公开(公告)号：WO2011046845A3

公开(公告)日：2011-08-18

申请号：PCT/US2010052115

申请日：2010-10-09

Applicant: RAMBUS INC ,  ARYANFAR FARSHID ,  LEE HAE-CHANG ,  CHANG KUN-YUNG ,  WU TING ,  WERNER CARL ,  KOOCHAKZADEH MASOUD

Inventor： ARYANFAR FARSHID ,  LEE HAE-CHANG ,  CHANG KUN-YUNG ,  WU TING ,  WERNER CARL ,  KOOCHAKZADEH MASOUD

IPC: H04L12/02

CPC classification number: H03L7/093 ,  G06F1/10 ,  H03L7/0802

Abstract: A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.

Abstract translation: 信号分配网络具有每个段具有缓冲电路，耦合到缓冲电路的传输线，通过传输线耦合到缓冲电路的电感器，以及耦合到电感器的可变电容电路，并通过 传输线。 可变电容电路的电容被设定为确定通过传输线传输的信号的相位和幅度。 信号分配网络可以包括相位检测器，环路滤波器电路和谐振延迟电路。 相位检测器将第一周期信号的相位与第二周期信号的相位进行比较。 谐振延迟电路具有可变阻抗电路，其具有基于环路滤波器电路的输出信号的变化而变化的阻抗。

公开(公告)号：WO2011090767A3

公开(公告)日：2011-10-06

申请号：PCT/US2010062615

申请日：2010-12-30

Applicant: RAMBUS INC ,  ARYANFAR FARSHID ,  LEE HAE-CHANG ,  WERNER CARL

Inventor： ARYANFAR FARSHID ,  LEE HAE-CHANG ,  WERNER CARL

IPC: H03L7/085

CPC classification number: H03L7/085 ,  G01R25/00 ,  H03D13/00 ,  H03L7/0816

Abstract: A phase detector circuit compares the phases of first and second periodic input signals to generate an output signal. The phase detector includes a circuit that makes two different combinations of the first and the second periodic input signals to generate third and fourth periodic signals. This circuit causes the third periodic signal to be based on a first combination of the first periodic signal and the second periodic signal that imparts a first relative phase shift. The circuit causes the fourth periodic signal to be based on a second combination of the first periodic signal and the second periodic signal to provide a different relative phase shift. The phase detector also includes a comparison circuit that compares a measure of the power of the third periodic signal to a measure of the power of the fourth periodic signal to generate the phase comparison output signal.

Abstract translation: 相位检测器电路比较第一和第二周期性输入信号的相位以产生输出信号。 相位检测器包括使第一和第二周期性输入信号的两种不同组合产生第三和第四周期性信号的电路。 该电路使得第三周期性信号基于赋予第一相对相移的第一周期性信号和第二周期性信号的第一组合。 该电路使得第四周期性信号基于第一周期性信号和第二周期性信号的第二组合以提供不同的相对相移。 相位检测器还包括比较电路，该比较电路将第三周期性信号的功率测量结果与第四周期性信号功率测量结果进行比较以生成相位比较输出信号。

公开(公告)号：WO2011059842A3

公开(公告)日：2011-08-18

申请号：PCT/US2010054900

申请日：2010-10-31

Applicant: RAMBUS INC ,  LEIBOWITZ BRIAN ,  LEE HAE-CHANG ,  ARYANFAR FARSHID ,  CHANG KUN-YUNG ,  SHEN JIE

Inventor： LEIBOWITZ BRIAN ,  LEE HAE-CHANG ,  ARYANFAR FARSHID ,  CHANG KUN-YUNG ,  SHEN JIE

IPC: H03L7/087 ,  G11C11/407

CPC classification number: H03D13/00 ,  H03L7/08 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/085

Abstract: A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.

Abstract translation: 相位检测电路可以包括两个相位检测器，每个相位检测器响应于同相对准的输入信号而产生非零输出。 输入信号基于两个周期信号。 相位检测电路从另一相位检测器的输出信号中减去一相位检测器的输出信号，当周期信号同相时产生具有零值的信号。 或者，相位检测器产生指示周期信号之间的相位差的相位比较信号。 相位比较信号响应于相位检测器的相位输入信号具有非零值。 输入信号基于周期信号。 输出电路接收相位比较信号，并响应于同相对齐的周期信号产生具有零值的输出。

公开(公告)号：WO2007114944A3

公开(公告)日：2007-11-29

申请号：PCT/US2007008493

申请日：2007-04-04

Applicant: RAMBUS INC ,  LEE HAE-CHANG ,  ZERBE JARED LEVAN ,  WERNER CARL WILLIAM

Inventor： LEE HAE-CHANG ,  ZERBE JARED LEVAN ,  WERNER CARL WILLIAM

IPC: H04L7/033

CPC classification number: H04L7/0278 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/091 ,  H03L2207/50 ,  H04L7/0008 ,  H04L7/0016 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0337 ,  H04L7/0338

Abstract: A circuit for performing clock recovery according to a received digital signal (30). The circuit includes at least an edge sampler (105) and a data sampler (145) for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock (25) and data clock (20) signals offset in phase from one another to the respective clock inputs of the edge sampler (105) and the data sampler (145). The clock signal supply circuit is operable to selectively vary a phase offset between the edge and data clock signals.

Abstract translation: 一种根据接收的数字信号执行时钟恢复的电路（30）。 该电路至少包括用于采样数字信号的边缘采样器（105）和数据采样器（145），以及时钟信号供应电路。 时钟信号提供电路提供彼此相位偏移到边缘采样器（105）和数据采样器（145）的相应时钟输入的边沿时钟（25）和数据时钟（20）信号。 时钟信号供应电路可操作以选择性地改变边沿与数据时钟信号之间的相位偏移。

公开(公告)号：WO2008076700A3

公开(公告)日：2008-12-11

申请号：PCT/US2007087027

申请日：2007-12-10

Applicant: RAMBUS INC ,  FRANS YOHAN U ,  LEE HAE-CHANG ,  LEIBOWITZ BRIAN S ,  LI SIMON ,  NGUYEN NHAT M

Inventor： FRANS YOHAN U ,  LEE HAE-CHANG ,  LEIBOWITZ BRIAN S ,  LI SIMON ,  NGUYEN NHAT M

IPC: H04L1/00 ,  G01R29/26 ,  H04B17/00 ,  H04L1/20 ,  H04L1/24 ,  H04L5/14

CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/4068 ,  H04L1/0002 ,  H04L1/0015 ,  H04L1/203 ,  H04L1/205 ,  H04L1/243 ,  H04L5/1446 ,  H04L25/0262 ,  H04L25/0292 ,  Y02B60/31 ,  Y02D50/10

Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined errorrate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

Abstract translation: 装置包括耦合到节点的发射器，其中节点将耦合到有线链路。 发射机具有多种操作模式，包括校准模式，其中根据与有线链路相对应的电压容限以预定误差率确定有线链路上的通信数据速率范围。 通信数据速率的范围包括最大数据速率，其可以是初始数据速率的非整数倍。

公开(公告)号：WO2009003129A3

公开(公告)日：2009-04-16

申请号：PCT/US2008068409

申请日：2008-06-26

Applicant: RAMBUS INC ,  LEE HAE-CHANG ,  REN JIHONG ,  LEIBOWITZ BRIAN S ,  MADDEN CHRISTOPHER J ,  LIN QI ,  ZERBE JARED L

Inventor： LEE HAE-CHANG ,  REN JIHONG ,  LEIBOWITZ BRIAN S ,  MADDEN CHRISTOPHER J ,  LIN QI ,  ZERBE JARED L

IPC: H04L25/02 ,  H04L1/20 ,  H04L25/03

CPC classification number: H04L25/03878 ,  H04L1/203 ,  H04L1/205 ,  H04L25/0224 ,  H04L25/0242 ,  H04L25/0264 ,  H04L25/0272 ,  H04L25/03012 ,  H04L25/03343

Abstract: A communication system supports high-speed communication over a signal lane that extends between respective transmitting and receiving integrated circuit (IC) devices. One or both of the IC devices includes an equalizer to offset channel characteristics that otherwise impair speed performance. A margining circuit on the receiving IC measures a timing margin of the received signal and adjusts the equalization settings for one or both transmitters to maximize the timing margin. Another embodiment compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex error analysis and adaptation circuitry on the higher-performance side of the lane. The error analysis and adaptation circuitry reduces the error margin of the transmitted signal to introduce bit errors at the receiver, analyzes the bit errors to measure ISI imposed by the channel, and adjusts voltage offsets of the continuous-time signal to compensate for the ISI. In some embodiments the receiver calculates the system response for diagnostics and for computing equalization settings.

Abstract translation: 通信系统支持在相应的发送和接收集成电路（IC）设备之间延伸的信号通道上的高速通信。 一个或两个IC器件包括均衡器以抵消否则会影响速度性能的通道特性。 接收IC上的边缘电路测量接收信号的定时裕度，并调整一个或两个发射机的均衡设置以使定时裕度最大化。 另一实施例通过在车道的较高性能侧实例化相对复杂的误差分析和适配电路来补偿通过双向通道通信的IC之间的性能不对称性。 误差分析和自适应电路减少发射信号的误差容限，在接收机引入位错误，分析位误差以测量通道施加的ISI，并调整连续时间信号的电压补偿以补偿ISI。 在一些实施例中，接收机计算用于诊断和计算均衡设置的系统响应。

公开(公告)号：WO2008063431A3

公开(公告)日：2008-11-13

申请号：PCT/US2007023600

申请日：2007-11-09

Applicant: RAMBUS INC ,  LEIBOWITZ BRIAN S ,  LEE HAE-CHANG ,  REN JIHONG ,  RATNAYAKE RUWAN

Inventor： LEIBOWITZ BRIAN S ,  LEE HAE-CHANG ,  REN JIHONG ,  RATNAYAKE RUWAN

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

Abstract: A device (102) implements data reception with edge-based partial response decision feedback equalization. The device implements a tap weight adapter circuit (114) that sets the tap weights that are used for adjustment of a received data -signal (104). The tap weight adapter circuit (114) sets the tap weights based. on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis (116) may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit (220) generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal is generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

Abstract translation: 设备（102）利用基于边缘的部分响应判决反馈均衡来实现数据接收。 该设备实现一个抽头权重适配器电路（114），其设置用于调整接收到的数据信号（104）的抽头权重。 抽头重量适配器电路（114）基于抽头权重设置。 使用一组边缘采样器对先前确定的数据值和来自接收数据信号的边缘分析的输入。 边缘分析（116）可以包括通过由抽头权重适配器电路确定的抽头权重来调整采样数据信号。 时钟发生电路（220）生成边沿时钟信号以控制由边缘采样器组执行的边缘采样。 边缘时钟信号是根据边缘采样器的信号和由均衡器确定的先前数据值产生的。

公开(公告)号：WO2010129873A3

公开(公告)日：2011-02-03

申请号：PCT/US2010034047

申请日：2010-05-07

Applicant: RAMBUS INC ,  CHANG KEN KUN-YUNG ,  PRABHU KASHINATH ,  LEE HAE-CHANG

Inventor： CHANG KEN KUN-YUNG ,  PRABHU KASHINATH ,  LEE HAE-CHANG

IPC: H03K19/0175 ,  H03K17/687

CPC classification number: H03K19/018585 ,  H03K19/018528

Abstract: A driver supports differential and single-ended signaling modes. Complementary transistors with a common tail node are provided with complementary input signals in the differential mode. A current source coupled to the tail node maintains a relatively high tail impedance and a constant tail current in the differential mode. The tail node is set to a low impedance in single-ended modes to decouple the two transistors, allowing them to amplify uncorrelated input signals. The current source draws multiple current levels in the single- ended mode to compensate for changes in tail current that result from changes in the relative values of the uncorrelated data in the single-ended modes. A termination block provides termination resistance in the differential mode, pull-up transistors in a single-ended mode that employs push-pull drivers, and is omitted in a single-ended mode that lacks driver-side termination.

Abstract translation: 驱动程序支持差分和单端信令模式。 具有公共尾节点的互补晶体管在差分模式下被提供有互补输入信号。 耦合到尾部节点的电流源在差分模式下保持相对高的尾部阻抗和恒定的尾部电流。 尾端节点在单端模式下设置为低阻抗，以对两个晶体管进行去耦，从而使它们能够放大不相关的输入信号。 电流源在单端模式下绘制多个电流电平，以补偿由单端模式中不相关数据的相对值变化引起的尾电流变化。 端接模块提供差分模式下的终端电阻，采用推挽驱动器的单端模式的上拉晶体管，并且在缺少驱动器侧端接的单端模式下省略。

公开(公告)号：WO2008070138A9

公开(公告)日：2009-03-05

申请号：PCT/US2007024948

申请日：2007-12-05

Applicant: RAMBUS INC ,  ZERBE JARED L ,  ASSADERAGHI FARIBORZ ,  LEIBOWITZ BRIAN S ,  LEE HAE-CHANG ,  REN JIHONG ,  LIN QI

Inventor： ZERBE JARED L ,  ASSADERAGHI FARIBORZ ,  LEIBOWITZ BRIAN S ,  LEE HAE-CHANG ,  REN JIHONG ,  LIN QI

IPC: H04L25/03

CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

Abstract: A transceiver architecture supports high-speed communication over a signal lane (120-125) that extends between a high-performance integrated circuit (IC) (105) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers (110). The. architecture compensates for performance asymmetry between ICs communicating over a bidirectional lan by instantiating relatively complex transmit (Tx1) and receive (Rx1) equalization cir.cuitry on the higher-performance, side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated (162) based upon the signal response at the receiver of the higher-performance IC (Rx1N).

Abstract translation: 收发机体系结构支持在高性能集成电路（IC）（105）和采用较不复杂的发射机和接收机（110）的一个或多个相对低性能的IC之间延伸的信号通道（120-125）上的高速通信。 。 的。 通过在更高性能的通道侧实例化相对复杂的发送（Tx1）和接收（Rx1）均衡电路，体系结构补偿了通过双向lan进行通信的IC之间的性能不对称。 基于在更高性能IC（Rx1N）的接收机处的信号响应，高性能IC中的发射和接收均衡滤波器系数都可以自适应地更新（162）。

公开(公告)号：WO2008070138A3

公开(公告)日：2009-01-15

申请号：PCT/US2007024948

申请日：2007-12-05

Applicant: RAMBUS INC ,  ZERBE JARED L ,  ASSADERAGHI FARIBORZ ,  LEIBOWITZ BRIAN S ,  LEE HAE-CHANG ,  REN JIHONG ,  LIN QI

Inventor： ZERBE JARED L ,  ASSADERAGHI FARIBORZ ,  LEIBOWITZ BRIAN S ,  LEE HAE-CHANG ,  REN JIHONG ,  LIN QI

IPC: H04L25/03

CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

Abstract: A transceiver architecture supports high-speed communication over a signal lane (120-125) that extends between a high-performance integrated circuit (IC) (105) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers (110). The. architecture compensates for performance asymmetry between ICs communicating over a bidirectional lan by instantiating relatively complex transmit (Tx1) and receive (Rx1) equalization cir.cuitry on the higher-performance, side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated (162) based upon the signal response at the receiver of the higher-performance IC (Rx1N).

Abstract translation: 收发器架构支持在高性能集成电路（IC）（105）和使用较不复杂的发送器和接收器（110）的一个或多个相对低性能的IC之间延伸的信号通道（120-125）上的高速通信， 。 的。 架构通过在车道的较高性能侧实例化相对复杂的发送（Tx1）和接收（Rx1）均衡电路来补偿通过双向LAN通信的IC之间的性能不对称性。 基于在高性能IC（Rx1N）的接收机处的信号响应，可以自适应地更新（162）高性能IC中的发射和接收均衡滤波器系数。