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    TIMING CALIBRATION FOR MULTIMODE I/O SYSTEMS
    1.
    发明申请
    TIMING CALIBRATION FOR MULTIMODE I/O SYSTEMS 审中-公开
    多模I / O系统的时序校准

    公开(公告)号：WO2012118714A2

    公开(公告)日：2012-09-07

    申请号：PCT/US2012026583

    申请日：2012-02-24

    Applicant: RAMBUS INC ,  OH KYUNG SUK ,  BANSAL AKASH

    Inventor： OH KYUNG SUK ,  BANSAL AKASH

    CPC classification number: G06F1/08 ,  G06F13/1689 ,  G11C7/1066 ,  G11C7/1093 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

    Abstract: Integrated circuit devices that operate in different modes. In a low data rate mode, data is transferred between the integrated circuit devices at a low data rate, or no data is transferred at all. In a high data rate mode, data is transferred between integrated circuit devices at a high data rate. A transition mode facilitates the transition from the low data rate mode to the high data rate mode. During the transition mode data is transferred between the integrated circuit devices at an intermediate data rate greater than the low data rate but lower than the high data rate. Also during the transition mode, parameters affecting the transmission of data between the integrated circuit devices are calibrated at the high data rate.

    Abstract translation: 在不同模式下工作的集成电路器件。 在低数据速率模式下，以低数据速率在集成电路设备之间传输数据，或完全没有数据传输。 在高数据速率模式下，以高数据速率在集成电路器件之间传输数据。 转换模式有助于从低数据速率模式转换到高数据速率模式。 在转换模式期间，以大于低数据速率但低于高数据速率的中间数据速率在集成电路器件之间传送数据。 而且在转换模式期间，在高数据速率下校准影响集成电路器件之间的数据传输的参数。

    RECEIVER FOR MULTI-WIRE COMMUNICATION WITH REDUCED INPUT CAPACITANCE
    2.
    发明申请
    RECEIVER FOR MULTI-WIRE COMMUNICATION WITH REDUCED INPUT CAPACITANCE 审中-公开
    具有降低输入电容的多线通信接收器

    公开(公告)号：WO2009086078A4

    公开(公告)日：2009-11-05

    申请号：PCT/US2008087639

    申请日：2008-12-19

    Applicant: RAMBUS INC ,  WARE FREDERICK ,  WILSON JOHN ,  OH KYUNG SUK ,  LEIBOWITZ BRIAN S ,  KIZER JADE M ,  LUO LEI

    Inventor： WARE FREDERICK ,  WILSON JOHN ,  OH KYUNG SUK ,  LEIBOWITZ BRIAN S ,  KIZER JADE M ,  LUO LEI

    IPC: G06F13/42 ,  H04L25/49

    CPC classification number: G06F13/4243 ,  H04L25/4906 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Embodiments of a device that receives and decodes a series of parallel symbol sets over a series of time intervals is described. In this device, symbols in a respective parallel symbol set are received on nodes. Each node receives a respective symbol, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). Differential amplifiers in the device provide primary comparison results, each of which compares symbols received on pairs of the links, and generation circuits in the device provide secondary comparison results from the primary comparison results. A decoder in the device decodes a respective parallel symbol set from the primary and secondary comparison results to recover encoded data.

    Abstract translation: 描述了通过一系列时间间隔接收和解码一系列并行符号集的设备的实施例。 在该装置中，各个并行符号组中的符号在节点上被接收。 每个节点接收相应的符号，其可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）。 器件中的差分放大器提供初步比较结果，每个比较结果比较了在链路对上接收到的符号，并且器件中的发生电路提供了主要比较结果的二次比较结果。 设备中的解码器从主要和次要比较结果解码相应的并行符号集合以恢复编码数据。

    METHODS AND SYSTEMS FOR REDUCING SUPPLY AND TERMINATION NOISE
    3.
    发明申请
    METHODS AND SYSTEMS FOR REDUCING SUPPLY AND TERMINATION NOISE 审中-公开
    减少供应和终止噪声的方法和系统

    公开(公告)号：WO2011041064A3

    公开(公告)日：2011-06-23

    申请号：PCT/US2010047466

    申请日：2010-09-01

    Applicant: RAMBUS INC ,  OH KYUNG SUK

    Inventor： OH KYUNG SUK

    IPC: G11C7/10

    CPC classification number: H03K19/0005 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2254

    Abstract: Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the first and second ICs and is terminated on both ends. The termination impedances at each end of the reference channel support different modes for communicating signals in different directions. The termination impedances for the reference channel can be optimized for each signaling direction.

    Abstract translation: 所描述的是第一集成电路（IC）中的通信系统通过单端通信信道与第二IC通信。 双向参考通道在第一和第二IC之间延伸并在两端终止。 参考通道每端的终端阻抗支持用于在不同方向上传送信号的不同模式。 参考通道的终端阻抗可针对每个信令方向进行优化。

    ASYMMETRIC COMMUNICATION ON SHARED LINKS
    4.
    发明申请
    ASYMMETRIC COMMUNICATION ON SHARED LINKS 审中-公开
    共享链路上的不对称通信

    公开(公告)号：WO2009086142A4

    公开(公告)日：2009-10-15

    申请号：PCT/US2008087743

    申请日：2008-12-19

    Applicant: RAMBUS INC ,  OH KYUNG SUK ,  WILSON JOHN ,  WARE FREDERICK ,  KIM WOOPOUNG ,  KIZER JADE M ,  LEIBOWITZ BRIAN S ,  LUO LEI ,  EBLE JOHN CRONAN

    Inventor： OH KYUNG SUK ,  WILSON JOHN ,  WARE FREDERICK ,  KIM WOOPOUNG ,  KIZER JADE M ,  LEIBOWITZ BRIAN S ,  LUO LEI ,  EBLE JOHN CRONAN

    IPC: G06F13/42 ,  H04L25/49

    CPC classification number: G06F13/4243 ,  H04L25/4906 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.

    Abstract translation: 描述了经由共享链路在两个设备之间传送双向数据的系统的实施例。 在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。 数据可以在传输之前被编码为一系列并行码字。 每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。 由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。 另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

    REDUCING UNWANTED REFLECTIONS IN SOURCE-TERMINATED CHANNELS
    7.
    发明申请
    REDUCING UNWANTED REFLECTIONS IN SOURCE-TERMINATED CHANNELS 审中-公开
    减少源终端信道中的未反映的反射

    公开(公告)号：WO2014015071A2

    公开(公告)日：2014-01-23

    申请号：PCT/US2013050945

    申请日：2013-07-17

    Applicant: RAMBUS INC

    Inventor： OH KYUNG SUK ,  VENKATESAN PRAVIN KUMAR ,  FRANS YOHAN USTHAVIA

    IPC: H04W88/02

    CPC classification number: G06F13/4221 ,  G06F13/28 ,  H04L25/0278 ,  H04L25/0298 ,  Y02B60/1228 ,  Y02B60/1235 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A memory controller and/or memory device control termination of a communication link in order to achieve power savings while reducing or eliminating unwanted reflections in the channel. Following transmission of data over the communication channel, termination is left enabled for a programmable time period beginning immediately following completion of the transmission. The time period is sufficiently long to allow the unwanted reflections to be absorbed by the termination. Following the time period, the termination is disabled for power savings.

    Abstract translation: 存储器控制器和/或存储器设备控制通信链路的终端，以便在减少或消除信道中的不必要的反射的同时实现功率节省。 在通过通信信道传输数据之后，在传输完成之后立即开始可编程时间段的终止。 该时间段足够长以允许不期望的反射被终端吸收。 在该时间段之后，终止功能被禁用以节省电力。

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