公开(公告)号：WO2021231120A1

公开(公告)日：2021-11-18

申请号：PCT/US2021/030444

申请日：2021-05-03

Applicant: QUALCOMM INCORPORATED

Inventor： SUH, Jungwon ,  CHUN, Dexter Tamio ,  SRINIVASAN, Anand ,  ALAVOINE, Olivier ,  MOLL, Laurent Rene

IPC: G06F11/10 ,  G06F11/1048 ,  G11C2029/1202 ,  G11C29/18 ,  G11C29/42 ,  G11C29/44 ,  G11C7/1045

Abstract: Methods and apparatuses for a system error-correction code function are presented. The apparatus includes a memory configured to communicate with a host via at least one data connection and at least one non-data connection. The memory includes a memory array. The memory array includes a first portion and a second portion. The memory is further configured to, in a first mode, store and output data in the first portion and the second portion of the memory array. The first portion is addressable by a first address, and the second portion is addressable by a second address. The memory is further configured to, in a second mode, receive ECC of the data from the host via the at least one non-data connection, store the data in the first portion of the memory array, and store the ECC of the data in the second portion of the memory array based on the first address.

公开(公告)号：WO2022094047A2

公开(公告)日：2022-05-05

申请号：PCT/US2021/057008

申请日：2021-10-28

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： ALAM, Syed, M. ,  JANESKY, Jason ,  LEE, Han, Kyu ,  ALMASI, Hamid ,  SANCHEZ, Pedro ,  MASGRAS, Cristian, P. ,  RAHMAN, Iftekhar ,  IKEGAWA, Sumio ,  AGGARWAL, Sanjeev ,  HOUSSAMEDDINE, Dimitri ,  NEUMEYER, Frederick, Charles

IPC: G06F11/16 ,  G06F11/1666 ,  G11C2029/0407 ,  G11C2029/1202 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/42 ,  G11C29/4401

Abstract: The present disclosure is drawn to, among other things, a method of managing a memory device. In some aspects, the method includes determining whether a first address for a page in a first memory region is mapped in a map table, setting a target address as a second address identified in the map table as being mapped to the first address, setting the target address as the first address, determining a number of bits that fail in each word of a plurality of first-layer error correction code (ECC) words for the target address, and adding the target address to the map table, writing-back contents from the target address to a repair address in the first memory region, and updating the map table by mapping the target address to the repair address.

公开(公告)号：WO2021127297A1

公开(公告)日：2021-06-24

申请号：PCT/US2020/065780

申请日：2020-12-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： CHIANG, Pin-Chuo ,  PICCARDI, Michele ,  PEKNY, Theodore T.

IPC: G11C29/02 ,  G11C29/50 ,  G11C27/02 ,  G08B29/06 ,  G08B29/123 ,  G11C2029/1202 ,  G11C27/026 ,  G11C29/024 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012 ,  G11C8/08 ,  H03K17/18

Abstract: The RC sensor circuit includes a driver circuit that includes an output configured to drive the RC sensor circuit to a drive voltage using a representative copy of a current that drives an electronic circuit line. The RC sensor circuit includes an integration capacitor. The integration capacitor is configured to integrate the representative copy of the current over a first time period to generate a first representative voltage and over a second time period to generate a second representative voltage. The RC sensor circuit includes a sampling circuit coupled to the integration capacitor. The sampling circuit is configured to determine a first sample voltage by sampling the first representative voltage and a second sample voltage by sampling the second representative voltage. A ratio of the first sample voltage and the second sample voltage is indicative of an RC time constant of the electronic circuit line.

公开(公告)号：WO2021127296A1

公开(公告)日：2021-06-24

申请号：PCT/US2020/065779

申请日：2020-12-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： CHIANG, Pin-Chuo ,  PICCARDI, Michele ,  PEKNY, Theodore T.

IPC: G11C29/02 ,  G11C29/50 ,  G04F10/04 ,  G08B29/06 ,  G08B29/123 ,  G11C2029/1202 ,  G11C27/026 ,  G11C29/024 ,  G11C29/025 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012 ,  G11C8/08 ,  H03H11/1291 ,  H03H7/0153

Abstract: A resistor-capacitor (RC) sensor circuit of an electronic device is driven to a drive voltage using a representative copy of a current that drives an electronic circuit line of the electronic device. The RC sensor circuit is to sample voltages that are indicative of an RC time constant of the electronic circuit line. A first sample voltage is determined by sampling a first representative voltage generated at the RC sensor circuit by driving the RC sensor circuit with the representative copy of the current over a first time period. A second sample voltage is determined by sampling a second representative voltage generated at the RC sensor circuit by driving the RC sensor circuit with the representative copy of the current over a second time period. A ratio of the first sample voltage and the second sample voltage is indicative of the RC time constant of the electronic circuit line.

公开(公告)号：WO2021222846A1

公开(公告)日：2021-11-04

申请号：PCT/US2021/030318

申请日：2021-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： CHIANG, Pinchou ,  MURALIDHARAN, Arvind ,  ESTEVES, James I. ,  PICCARDI, Michele ,  PEKNY, Theodore T.

IPC: G11C29/02 ,  G11C29/12 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  G11C2029/1202 ,  G11C29/025 ,  G11C8/08

Abstract: A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition.

公开(公告)号：WO2021134093A1

公开(公告)日：2021-07-01

申请号：PCT/US2020/070869

申请日：2020-12-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： XU, Dan ,  XU, Jun ,  YU, Erwin E. ,  TESSARIOL, Paolo ,  IWASAKI, Tomoka Ogura

IPC: G11C8/14 ,  G11C29/02 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  G11C16/08 ,  G11C29/12 ,  G11C29/24 ,  G11C29/44 ,  H01L27/115 ,  G11C29/54 ,  G11C13/003 ,  G11C13/0038 ,  G11C16/0483 ,  G11C2029/1202 ,  G11C2029/4402 ,  G11C29/025 ,  G11C29/028 ,  G11C5/025 ,  G11C5/063 ,  G11C5/066

Abstract: Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.