公开(公告)号：WO2023273110A1

公开(公告)日：2023-01-05

申请号：PCT/CN2021/132274

申请日：2021-11-23

Applicant: 颀中科技（苏州）有限公司 ,  合肥颀中科技股份有限公司

Inventor： 许冠猛

IPC: H01L21/02 ,  H01L21/02109 ,  H01L21/02112 ,  H01L21/02299

Abstract: 本发明提供晶圆表面介电层的制备方法、晶圆结构及凸块的成型方法，制备方法包括：提供晶圆；在晶圆上形成对位标记，对位标记厚度不低于0.3μm；在形成对位标记后的晶圆上形成介电层。本申请在晶圆表面成型出介电层前，预先在晶圆表面制出对位标记。避免在介电层制备阶段因对位标记不可见而需返工，保障了制程的连续性。

公开(公告)号：WO2021257185A1

公开(公告)日：2021-12-23

申请号：PCT/US2021/029214

申请日：2021-04-26

Applicant: APPLIED MATERIALS, INC.

Inventor： GARCIA DE GORORDO, Alvaro ,  YAO, Zhonghua ,  SRINIVASAN, Sunil ,  PARK, Sang Wook

IPC: H01L21/3065 ,  H01L21/308 ,  B81C2201/0138 ,  H01L21/02112 ,  H01L21/02263 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/30655 ,  H01L21/3086 ,  H01L21/31116

Abstract: A method for etching silicon at cryogenic temperatures is provided. The method includes forming an inert layer from condensation of a noble gas at cryogenic temperatures on exposed surfaces such as the sidewalls of a feature to passivate the sidewalls prior to the etching process. The method further includes flowing a fluorine- containing precursor gas into the chamber to form a fluorine-containing layer on the inert layer. The method further includes exposing the fluorine-containing layer and the inert layer to an energy source to form a passivation layer on the exposed portions of the substrate and exposing the substrate to ions to etch the substrate.

公开(公告)号：WO2022031485A1

公开(公告)日：2022-02-10

申请号：PCT/US2021/043376

申请日：2021-07-28

Applicant: APPLIED MATERIALS, INC.

Inventor： WANG, Huiyuan ,  KUSTRA, Rick ,  QI, Bo ,  MALLICK, Abhijit Basu ,  ALAYAVALLI, Kaushik ,  PINSON, Jay D.

IPC: H01L21/02 ,  H01L21/033 ,  C23C16/30 ,  C23C16/448 ,  C23C16/505 ,  C23C16/32 ,  C23C16/342 ,  C23C16/345 ,  C23C16/36 ,  C23C16/401 ,  C23C16/50 ,  H01L21/02112 ,  H01L21/02129 ,  H01L21/0217 ,  H01L21/02205 ,  H01L21/02208 ,  H01L21/02274 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262

Abstract: Examples of the present technology include semiconductor processing methods to form boron-containing materials on substrates. Exemplary processing methods may include delivering a deposition precursor that includes a boron-containing precursor to a processing region of a semiconductor processing chamber. A plasma may be formed from the deposition precursor within the processing region of the semiconductor processing chamber. The methods may further include depositing a boron-containing material on a substrate disposed within the processing region of the semiconductor processing chamber, where the substrate is characterized by a temperature of less than or about 50 °C. The as-deposited boron-containing material may be characterized by a surface roughness of less than or about 2 nm, and a stress level of less-than or about -500 MPa. In some embodiments, a layer of the boron-containing material may function as a hardmask.

公开(公告)号：WO2021195997A1

公开(公告)日：2021-10-07

申请号：PCT/CN2020/082533

申请日：2020-03-31

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： PENG, Shuangshuang ,  GENG, Jingjing ,  WU, Jiajia ,  LI, Tuo

IPC: H01L27/115 ,  H01L21/02112 ,  H01L21/02178 ,  H01L21/28238 ,  H01L27/1157 ,  H01L27/11582

Abstract: A 3D memory devices and a method for forming the same are disclosed. The 3D memory device includes a substrate (302), a memory stack (304A, 304B) including interleaved conductive layers and dielectric layers above the substrate (302), and a channel structure extending vertically through the memory stack (304A, 304B). The channel structure includes a high dielectric constant (high-k) dielectric layer (312) disposed continuously along a sidewall of the channel structure, a memory film over the high-k dielectric layer (312) along the sidewall of the channel structure, and a semiconductor channel over the memory film along the sidewall of the channel structure.