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    IC GERMANIUM INSULATOR SUBSTRATE AND METHOD OF MANUFACTURE OF IC SUBSTRATE
    2.
    发明申请
    IC GERMANIUM INSULATOR SUBSTRATE AND METHOD OF MANUFACTURE OF IC SUBSTRATE 审中-公开
    IC绝缘子基板和IC基板的制造方法

    公开(公告)号：WO2007148072A3

    公开(公告)日：2008-03-27

    申请号：PCT/GB2007002281

    申请日：2007-06-19

    Applicant: UNIV BELFAST ,  GAMBLE HAROLD SAMUEL ,  AMSTRONG BRIAN MERVYN ,  MCNEILL DAVID WILLIAM ,  MITCHELL NEIL SAMUEL JOHN

    Inventor： GAMBLE HAROLD SAMUEL ,  AMSTRONG BRIAN MERVYN ,  MCNEILL DAVID WILLIAM ,  MITCHELL NEIL SAMUEL JOHN

    IPC: H01L21/762 ,  H01L21/86 ,  H01L27/12 ,  H01L29/786

    CPC classification number: H01L21/76254 ,  H01L21/86 ,  H01L27/1203 ,  H01L29/78603 ,  H01L29/78684

    Abstract: An integrated circuit (IC) substrate (32) comprising a germanium layer (26), an aluminium oxide layer (22), and an interfacial layer (28) provided on the germanium layer between the germanium layer and the aluminium oxide layer, which interfacial layer provides control of electrical properties at an interface between the germanium layer and the interfacial layer. The electrical properties may comprise charge carrier trap density, and the interfacial layer may provide control of the charge carrier trap density to minimise the trap density. The interfacial layer is used to ensure an intimate, high-quality germanium layer - interfacial layer interface. A method manufacturing an IC substrate is also provided, along with a gallium arsenide circuit integrated in a system-on-chip (SOC) comprising an IC substrate, and a germanium electronic circuit in combination with a gallium arsenide circuit, integrated in a system-on-chip- (SOC), comprising an IC substrate.

    Abstract translation: 一种包括锗层（26），氧化铝层（22）和设置在锗层和氧化铝层之间的锗层上的界面层（28）的集成电路（IC）基板，其界面 层提供了在锗层和界面层之间的界面处的电性质的控制。 电性能可以包括电荷载流子阱密度，并且界面层可以提供电荷载流子阱密度的控制以最小化陷阱密度。 界面层用于确保密实，高质量的锗层 - 界面层界面。 还提供了一种制造IC基板的方法，以及集成在包括IC基板的片上系统（SOC）中的砷化镓电路和与砷化镓电路组合的锗电子电路， 片上（SOC），包括IC衬底。

    SUBSTRATE-TRANSFERRED, DEEP TRENCH ISOLATION SILICON-ON-INSULATOR (SOI) SEMICONDUCTOR DEVICES FORMED FROM BULK SEMICONDUCTOR WAFERS
    4.
    发明申请
    SUBSTRATE-TRANSFERRED, DEEP TRENCH ISOLATION SILICON-ON-INSULATOR (SOI) SEMICONDUCTOR DEVICES FORMED FROM BULK SEMICONDUCTOR WAFERS 审中-公开
    基板转移，深度分离隔离硅片绝缘体（SOI）半导体器件从块状半导体波形

    公开(公告)号：WO2017048531A1

    公开(公告)日：2017-03-23

    申请号：PCT/US2016/050068

    申请日：2016-09-02

    Applicant: QUALCOMM INCORPORATED

    Inventor： KIM, Daeik, Daniel ,  YUN, Changhan, Hobie ,  LAN, Je-Hsiung, Jeffrey ,  KIM, Jonghae ,  NOWAK, Matthew, Michael

    IPC: H01L21/84 ,  H01L21/86 ,  H01L21/762 ,  H01L29/786 ,  H01L27/12

    CPC classification number: H01L27/1203 ,  H01L21/76256 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/86

    Abstract: Substrate-transferred, deep trench isolation silicon-on-insulator (SOI) semiconductor devices formed from bulk semiconductor wafers are disclosed. In this regard, a bulk semiconductor wafer is provided that includes a bulk body, one or more transistors formed in the bulk body, and deep trenches formed between the transistors formed in the bulk body to provide isolation between the transistors. To prevent the bulk body from electrically interconnecting the transistors, the bulk body is thinned near, at, or beyond a back side of the deep trenches formed in the bulk body to form separate bulk bodies for each transistor isolated by the deep trenches. An insulation substrate is bonded to the bulk semiconductor device to form an SOI wafer. In this manner, residual bulk bodies of the transistors in the SOI wafer are isolated between the deep trenches and the insulation substrate to reduce or avoid leakage current between transistors.

    Abstract translation: 公开了由体半导体晶片形成的衬底转移的深沟槽隔离绝缘体上硅（SOI）半导体器件。 在这方面，提供了体积半导体晶片，其包括体本体，在体本体中形成的一个或多个晶体管，以及形成在体本体中形成的晶体管之间的深沟槽，以提供晶体管之间的隔离。 为了防止体本体电连接晶体管，体本体在形成于体本体中的深沟槽的背面附近，之中或之上变薄，以形成用于由深沟槽隔离的每个晶体管的分离体。 将绝缘基板接合到体半导体器件以形成SOI晶片。 以这种方式，SOI晶片中的晶体管的残余块体在深沟槽和绝缘衬底之间被隔离，以减少或避免晶体管之间的漏电流。

    HETEROGENEOUS SUBSTRATE, NITRIDE-BASED SEMICONDUCTOR DEVICE USING SAME AND MANUFACTURING METHOD THEREOF
    8.
    发明申请
    HETEROGENEOUS SUBSTRATE, NITRIDE-BASED SEMICONDUCTOR DEVICE USING SAME AND MANUFACTURING METHOD THEREOF 审中-公开
    非均匀衬底，使用该衬底的氮化物基半导体器件及其制造方法

    公开(公告)号：WO2010147357A3

    公开(公告)日：2011-03-03

    申请号：PCT/KR2010003828

    申请日：2010-06-15

    Applicant: KOREA ELECTRONICS TECHNOLOGY ,  HWANG SUNG MIN ,  BAIK KWANG HYEON ,  SEO YONG GON ,  YOON HYUNG DO ,  PARK JAE HYOUN

    Inventor： HWANG SUNG MIN ,  BAIK KWANG HYEON ,  SEO YONG GON ,  YOON HYUNG DO ,  PARK JAE HYOUN

    IPC: H01L21/20 ,  H01L21/86

    CPC classification number: H01L21/0254 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02639 ,  H01L33/007 ,  H01L33/22

    Abstract: The present invention relates to a heterogeneous substrate, to a nitride-based semiconductor device using the same and to a manufacturing method thereof. The present invention adjusts the mode of crystal growth to form a high quality non-polar or semi-polar nitride layer on a non-polar plane or a semi-polar plane of the heterogeneous substrate. The method according to the present invention prepares a base substrate having either a non-polar plane or a semi-polar plane, and forms a nitride-based crystal growth core layer on the plane of the prepared base substrate. A first buffer layer is grown on the crystal growth core layer such that the first buffer layer is grown faster in a vertical direction than in a horizontal direction. A horizontal growing layer is grown on the first buffer layer such that the horizontal growing layer is grown faster in a horizontal direction than in a vertical direction. Subsequently, a second buffer layer is grown on the horizontal growing layer. Here, a nitride silicon layer having a plurality of holes can be further formed between the horizontal growing layer on the first buffer layer and the second buffer layer.

    Abstract translation: 本发明涉及异质衬底，涉及使用其的氮化物基半导体器件及其制造方法。 本发明调整晶体生长的模式以在非均质衬底的非极性平面或半极性平面上形成高质量的非极性或半极性氮化物层。 根据本发明的方法制备具有非极性平面或半极性平面的基础衬底，并且在所制备的基础衬底的平面上形成基于氮化物的晶体生长芯层。 在晶体生长核心层上生长第一缓冲层，使得第一缓冲层在垂直方向上比在水平方向上生长得更快。 在第一缓冲层上生长水平生长层，使得水平生长层在水平方向上比在垂直方向上生长得更快。 随后，在水平生长层上生长第二缓冲层。 这里，可以在第一缓冲层上的水平生长层和第二缓冲层之间进一步形成具有多个孔的氮化硅层。

    이종 기판, 그를 이용한 질화물계 반도체 소자 및 그의 제조 방법
    9.
    发明申请
    이종 기판, 그를 이용한 질화물계 반도체 소자 및 그의 제조 방법 审中-公开

    公开(公告)号：WO2010147357A4

    公开(公告)日：2010-12-23

    申请号：PCT/KR2010/003828

    申请日：2010-06-15

    Applicant: 전자부품연구원 ,  황성민 ,  백광현 ,  서용곤 ,  윤형도 ,  박재현

    Inventor： 황성민 ,  백광현 ,  서용곤 ,  윤형도 ,  박재현

    IPC: H01L21/20 ,  H01L21/86

    Abstract: 본 발명은 이종 기판, 그를 이용한 질화물계 반도체 소자 및 그의 제조 방법에 관한 것으로, 이종 기판의 무극성 또는 반극성면에 결정 성장 모드를 조절하여 고품질의 무극성 또는 반극성 질화물층을 형성하기 위한 것이다. 본 발명에 따르면, 무극성 또는 반극성면 중에 하나를 갖는 베이스 기판을 준비하고, 준비된 베이스 기판의 면에 질화물계 결정성장핵층을 형성한다. 결정성장핵층 위에 제1 버퍼층을 성장시키되, 수평 방향에 비해서 수직 방향으로 더 빨리 성장시킨다. 제1 버퍼층 위에 수평성장층을 성장시키되, 수직 방향에 비해서 수평 방향으로 더 빨리 성장시킨다. 그리고 수평성장층 위에 제2 버퍼층을 성장시킨다. 이때 제1 버퍼층 위의 수평성장층과 제2 버퍼층 사이에 복수의 구멍을 갖는 질화실리콘층을 더 형성할 수 있다.

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