公开(公告)号：WO2005057631A2

公开(公告)日：2005-06-23

申请号：PCT/US2004039970

申请日：2004-11-30

Applicant: IBM ,  DE SOUZA JOEL P ,  OTT JOHN A ,  REZNICEK ALEXANDER ,  SAENGER KATHERINE L

Inventor： DE SOUZA JOEL P ,  OTT JOHN A ,  REZNICEK ALEXANDER ,  SAENGER KATHERINE L

IPC: H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L29/10 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/78696 ,  H01L21/2022 ,  H01L21/76251 ,  H01L21/76275 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/66772 ,  H01L29/78654

Abstract: A method utilizing localized amorphization and recrystallization of stacked template layers is provided for making a planar substrate having semiconductor layers of different crystallographic orientations. Also provided are hybrid­-orientation semiconductor substrate structures built with the methods of the invention, as well as such structures integrated with various CMOS circuits comprising at least two semiconductor devices disposed on different surface orientations for enhanced device performance.

Abstract translation: 提供了利用层叠模板层的局部非晶化和重结晶的方法，用于制造具有不同晶体取向的半导体层的平面基板。 还提供了利用本发明的方法构建的混合取向半导体衬底结构，以及与各种CMOS电路集成的这种结构，其包括设置在不同表面取向上的至少两个半导体器件，用于增强器件性能。

公开(公告)号：WO03105189A2

公开(公告)日：2003-12-18

申请号：PCT/US0318007

申请日：2003-06-06

Applicant: AMBERWAVE SYSTEMS CORP

Inventor： LOCHTEFELD ANTHONY J ,  LANGDO THOMAS A ,  HAMMOND RICHARD ,  CURRIE MATTHEW T ,  BRAITHWAITE GLYN ,  FITZGERALD EUGENE A

IPC: H01L21/20 ,  H01L21/331 ,  H01L21/336 ,  H01L21/337 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L

CPC classification number: H01L29/785 ,  H01L21/76254 ,  H01L21/76259 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66242 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/66916 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78684 ,  H01L29/78687

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract translation: 应变半导体的优点与基板和器件制造上的绝缘体绝缘体方法相结合。

公开(公告)号：WO01084602A2

公开(公告)日：2001-11-08

申请号：PCT/US2001/040620

申请日：2001-04-27

IPC: H01L21/762 ,  H01L21/00

CPC classification number: H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76286

Abstract: A method of forming a shallow-deep trench isolation (SDTI) is provided that includes the steps of forming a pair of deep trenches through a silicon on insulator (SOI) layer without substantially disturbing an underlying buried oxide (BOX) layer. Once the deep trenches are formed, the trenches are formed, the trenches are filed with suitable electrical isolating materials, such as undoped poly-silicon or dielectric material, and etched back to obtain a substantially planarized top surface. Subsequently, an active nitride layer is deposited on the planarized top surface, and then a pair of shallow trenches are formed. The shallow trenches are formed using a low selectively etch to uniformly etch a deep trench liner oxide, the SOI layer and the electrical isolating material which have interfaces at non-perpendicular angles with respect to the direction of the etching. Once the shallow and deep trenches are formed, subsequent processing including filling the shallow trench, annealing and chemical-mechanical polishing can be performed.

Abstract translation: 提供了形成浅深沟槽隔离（SDTI）的方法，其包括以下步骤：通过绝缘体上硅（SOI）层形成一对深沟槽，而不会基本上干扰下面的掩埋氧化物（BOX）层。 一旦形成了深沟槽，则形成沟槽，沟槽用合适的电绝缘材料（例如未掺杂的多晶硅或电介质材料）放置并且被回蚀以获得基本平坦化的顶表面。 随后，在平坦化的顶表面上沉积活性氮化物层，然后形成一对浅沟槽。 使用低选择性蚀刻来形成浅沟槽以均匀蚀刻深沟槽衬垫氧化物，SOI层和电绝缘材料，其具有相对于蚀刻方向以非垂直角度的界面。 一旦形成浅沟槽和深沟槽，就可以执行包括填充浅沟槽，退火和化学机械抛光的后续处理。

公开(公告)号：WO1996009648A1

公开(公告)日：1996-03-28

申请号：PCT/EP1995003697

申请日：1995-09-19

Applicant: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V. ,  PLETTNER, Andreas ,  HABERGER, Karl

Inventor： FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.

IPC: H01L25/065

CPC classification number: H01L21/76264 ,  H01L21/2007 ,  H01L21/76275 ,  H01L21/76283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for producing a semiconductor structure with a highly conductive buried layer with the steps: application of an insulating layer (22) to a first surface of a first semiconductor substrate (23); application of an insulating layer (29) on a surface of a layer (28) of highly conductive material which is physically separate from the first semiconductor substrate; and bonding the two insulation layers.

Abstract translation: 一种用于制造半导体结构与以下步骤的高导电性埋层过程：在第一半导体衬底（23）的第一表面上施加绝缘层（22），其由高导电材料层组成的组中的一个表面上施加绝缘层（22）（28 ），其在物理上与第一半导体基板分离，并且连接两个绝缘层。

公开(公告)号：WO1994023444A2

公开(公告)日：1994-10-13

申请号：PCT/US1994003855

申请日：1994-04-01

Applicant: HARRIS CORPORATION

Inventor： HARRIS CORPORATION ,  LINN, Jack, H. ,  LOWRY, Robert, K. ,  ROUSE, George, V. ,  BULLER, James, F.

IPC: H01L21/20

CPC classification number: H01L21/76264 ,  H01L21/2007 ,  H01L21/76275 ,  H01L21/76286 ,  H01L27/1203

Abstract: Low temperature wafer bonding using a chemically reacting material between wafers to form a bonded zone to bond two wafers together. Examples include silicon wafers with a silicon-oxidizing bonding liquid which also permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Silicon wafers also may use solid reactants which include deposited layers of metal and polysilicon to form silicide bonded zones. Oxidizers such as nitric acid may be used in the bonding liquid, and a bonding liquid may be used in conjunction with a solid bonding reactant. Dielectric layers on silicon wafers may be used when additional silicon is provided for the bonding reactions. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening and buried resistors.

Abstract translation: 使用晶片之间的化学反应材料进行低温晶片接合，以形成将两个晶片结合在一起的结合区域。 实例包括具有硅氧化粘合液体的硅晶片，其也允许引入辐射固化掺杂剂和电活性掺杂剂作为粘合液体的组分。 硅晶片还可以使用固体反应物，其包括金属和多晶硅的沉积层以形成硅化物结合区。 可以在接合液中使用硝酸等氧化剂，结合液可以与固体键合反应物结合使用。 当为粘合反应提供额外的硅时，可以使用硅晶片上的介电层。 由这种接合晶片制造的集成电路可以具有掩埋层和辐射硬化和掩埋电阻。

公开(公告)号：WO2012068777A1

公开(公告)日：2012-05-31

申请号：PCT/CN2011/001926

申请日：2011-11-18

Applicant: 复旦大学 ,  王鹏飞 ,  林曦 ,  张卫

Inventor： 王鹏飞 ,  林曦 ,  张卫

IPC: H01L21/60

CPC classification number: H01L29/66333 ,  H01L21/76275 ,  H01L29/41741

公开(公告)号：WO2009032582A1

公开(公告)日：2009-03-12

申请号：PCT/US2008/074178

申请日：2008-08-25

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  PINTO, Angelo ,  CHIDAMBARAM, Periannan, R. ,  WISE, Rick, L.

Inventor： PINTO, Angelo ,  CHIDAMBARAM, Periannan, R. ,  WISE, Rick, L.

IPC: H01L21/762

CPC classification number: H01L21/76275 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/045

Abstract: A device (2300) and method of reducing residual STI corner defects in a hybrid orientation transistor comprising, forming a direct silicon bonded substrate (2002) wherein a second silicon layer with a second crystal orientation is bonded to a handle substrate with a first crystal orientation, forming a pad oxide (2102) layer on the second silicon layer, forming a nitride layer (2104) on the pad oxide layer, forming an isolation trench (2206) within the direct silicon bonded substrate through the second silicon layer and into the handle substrate, patterning a PMOS region of the direct silicon bonded substrate utilizing photoresist (2302) including a portion of the isolation trench, implanting (2304) and amorphizing an NMOS region of the direct silicon bonded substrate, removing the photoresist, performing solid phase epitaxy, performing a recrystallization anneal, forming an STI liner, completing front end processing, and performing back end processing.

Abstract translation: 一种减少混合取向晶体管中的残留STI拐角缺陷的装置（2300）和方法，包括：形成直接硅键合衬底（2002），其中具有第二晶体取向的第二硅层以第一晶体取向结合到手柄衬底 ，在所述第二硅层上形成衬垫氧化物层（2102），在所述衬垫氧化物层上形成氮化物层（2104），通过所述第二硅层在所述直接硅键合衬底内形成隔离沟槽（2206）并进入所述手柄 衬底，利用包括隔离沟槽的一部分的光致抗蚀剂（2302）构图直接硅键合衬底的PMOS区域，注入（2304）并使直接硅键合衬底的NMOS区域非晶化，去除光致抗蚀剂，进行固相外延， 进行再结晶退火，形成STI衬垫，完成前端处理，以及进行后端处理。

公开(公告)号：WO2002078075A1

公开(公告)日：2002-10-03

申请号：PCT/BE2002/000043

申请日：2002-03-25

Applicant: UNIVERSITÉ CATHOLIQUE DE LOUVAIN ,  FLANDRE, Denis ,  NEVE de MEVERGNIES, Amaury ,  RASKIN, Jean-Pierre

Inventor： FLANDRE, Denis ,  NEVE de MEVERGNIES, Amaury ,  RASKIN, Jean-Pierre

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L21/76256 ,  H01L21/76264 ,  H01L21/76275 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78603

Abstract: The present invention relates to a method for fabrication of semiconductor devices, in particular but not limited to the fabrication of double gate transistors of the type Gate-All-Around or "semiconductor-on-nothing" transistors and devices. A method according to the present invention comprises the steps of: (a) forming a trench in a least a first substrate, (b) transferring semiconductor material over the trench to form a semiconductor bridge across the trench, the semiconductor bridge defining an active area. The bridge may be free to oscillate above the trench without using removing a sacrificial layer. The method may also include the steps of: (c) forming a gate insulator on the semiconductor bridge, and (d) applying gate material on the gate insulator, thus forming a gate.

Abstract translation: 本发明涉及一种制造半导体器件的方法，特别是但不限于制造栅型全能型或“无半导体器件”晶体管和器件的双栅极晶体管。 根据本发明的方法包括以下步骤：（a）在至少第一衬底中形成沟槽，（b）将半导体材料转移到所述沟槽上以在所述沟槽上形成半导体桥，所述半导体桥限定有源区 。 桥可以自由地在沟槽上方振荡，而不用去除牺牲层。 该方法还可以包括以下步骤：（c）在半导体电桥上形成栅极绝缘体，以及（d）在栅极绝缘体上施加栅极材料，从而形成栅极。

公开(公告)号：WO99053541A1

公开(公告)日：1999-10-21

申请号：PCT/DE1999/000247

申请日：1999-01-29

IPC: H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/0623 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L29/0634 ,  H01L29/7841 ,  H01L29/78624

Abstract: The invention relates to a method for producing an SOI (silicon on insulator) wafer for low-impedance high-voltage semiconductor components which comprises the following steps: (a) producing a semiconductor wafer (1) from a semiconductor substrate (2) on whose upper side a plurality of epitaxial layers (3, 4, 5) are provided; (b) inserting trenches (6) in the epitaxial layers (3, 4, 5) and a marking groove (7) which extends to the semiconductor substrate (2); (c) depositing a polycrystalline silicon layer (8) on the surface of the uppermost epitaxial layer (5), the trenches (6) and the marking groove (7), said silicon layer being doped with a dopant of a first conduction type; (d) directly bonding the surface of the uppermost epitaxial layer (5), said surface being provided with the doped polycrystalline silicon layer (8), with the upper side of an additional semiconductor wafer (10), said upper side being provided with an insulating layer (11), and removing the semiconductor substrate (2) from the other upper side thereof; (e) inserting additional trenches (16) in the lowest epitaxial layer (3) from the cut upper surface until the base of the trenches (6) is reached, and applying an additional polycrystalline silicon layer (15), said layer being doped with a dopant of the first conduction type, on the walls of the additional trenches (16) such that continuous trenches (6, 16) are produced, and; (f) filling the continuous trenches (6, 16) with insulating material (14).

Abstract translation: 本发明涉及一种方法，用于制造SOI晶片的低高压半导体器件，其包括以下步骤：（a）从半导体基板（2）形成的半导体晶片（1），上的多个外延层（3，4的上表面， 5）被提供; （B）在所述外延层中引入沟槽（6）（3，4，5）和所述半导体基板，实现（2）标记槽（7）; （C）具有一种导电类型的掺杂的多晶硅层（8）的最上面的外延层的表面上的掺杂剂沉积（5），所述沟槽（6）和标记槽（7）; （D）在掺杂的多晶硅层的直接键合（8）提供（5）设置有另一半导体晶片的有绝缘层（11）顶部（10）和除去其他顶部的半导体衬底（2）的顶部外延层的表面 ; （E）引入在底部外延层进一步沟槽（16）的（3）烧蚀表面，直到达到所述沟槽（6）的底部，并施加与所述第一导电类型的进一步的多晶硅层的掺杂剂掺杂（15） 进一步沟槽（16），以使得连续槽的壁（6，16）被形成; 连续的槽（6,16）用绝缘材料（14）的和（f）灌装。

公开(公告)号：WO99001899A1

公开(公告)日：1999-01-14

申请号：PCT/JP1998/002918

申请日：1998-06-30

IPC: G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/02 ,  H01L21/20 ,  H01L21/336 ,  H01L21/762 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1266 ,  B23K26/0063 ,  B23K26/40 ,  B23K2203/172 ,  G02F1/13454 ,  G02F1/1362 ,  H01L21/2007 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/76289 ,  H01L27/1214 ,  H01L29/78603 ,  H01L2221/68359 ,  H01L2221/68368

Abstract: A method of manufacturing thin film devices comprising the steps of transferring a thin film device formed on a substrate onto a primary transfer body and then transferring it onto a secondary transfer body. A first isolation layer (120) such as amorphous silicon is provided over a substrate (100) that can transmit a laser beam. Over the substrate (100) is formed a thin film device (140) such as TFT, over which a second isolation layer (160) such as thermally fusible adhesive layer is formed. A primary transfer body (180) is formed over the second isolation layer. Light is applied to the resultant product to weaken the bonding force of the first isolation layer so that the substrate (100) can be removed to thereby transfer the thin film device (140) onto the primary transfer body (180). Further, a secondary transfer body (200) is bonded to the underside of the exposed thin film device (140) through an adhesive layer (190). The second isolation layer is then thermally fused to weaken its bonding force and the primary transfer body is removed. As a result, the thin film device (140) is transferred onto the secondary transfer body (200) while maintaining the same relation as the lamination relation with the substrate (100).

Abstract translation: 一种制造薄膜器件的方法，包括以下步骤：将形成在衬底上的薄膜器件转移到一次转印体上，然后将其转印到二次转印体上。 诸如非晶硅的第一隔离层（120）设置在可以透射激光束的衬底（100）上。 在基板（100）上形成诸如TFT的薄膜器件（140），在其上形成诸如热熔粘合剂层的第二隔离层（160）。 在第二隔离层上形成一次转印体（180）。 对所得产品施加光以减弱第一隔离层的结合力，从而可以去除衬底（100），从而将薄膜器件（140）转移到一次转印体（180）上。 此外，二次转印体（200）通过粘合剂层（190）结合到暴露的薄膜器件（140）的下侧。 然后将第二隔离层热熔融以削弱其结合力，并且去除一次转印体。 结果，薄膜器件（140）被转印到二次转印体（200）上，同时保持与基底（100）的层叠关系相同的关系。