公开(公告)号：WO2015040202A1

公开(公告)日：2015-03-26

申请号：PCT/EP2014/070082

申请日：2014-09-22

Applicant: ABB TECHNOLOGY AG

Inventor： BAUER, Friedhelm

IPC: H01L29/745 ,  H01L29/749 ,  H01L29/06

CPC classification number: H01L29/7455 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/0847 ,  H01L29/1012 ,  H01L29/1095 ,  H01L29/41716 ,  H01L29/749

Abstract: A power semiconductor device (1) is provided comprising, in the following order: - a collector electrode (1), - a collector layer (2) of a second conductivity type, - a drift layer (3) of a first conductivity type, - a base layer (4) of the second conductivity type, - a first insulating layer (8) having an opening (82), - an emitter layer (5) of the first conductivity type, wherein the emitter layer (5) is in contact with the base layer (4) and separated from the drift layer (3) at least by one of the first insulating layer (8) or the base layer (4), - a body layer (6) of the second conductivity type arranged laterally to the emitter layer (5) and separated from the base layer (4) by the first insulating layer (8) and the emitter layer (5), - a source region (7) of the first conductivity type separated from the emitter layer (5) by the body layer (6), - an emitter electrode (15) contacted by the source region (7). The device further comprises a first layer (65) of the second conductivity type in contact with the emitter electrode (15) and separated from the base layer (4), and a second layer (55) of the first conductivity type arranged between the first layer (65) and the base layer (4) and separated from the emitter layer (5) and the source region (7). A planar MIS gate electrode (9) is arranged laterally from the emitter electrode (15), a corresponding MIS channel being formable between the source region (7), the body layer (6) and the emitter layer (5). A thyristor current path (120) extends between the emitter layer (5), the base layer (4) and the drift layer (3) through the opening (82), and a turn-off MIS channel (110) is formable below the planar MIS gate electrode (9) from the first layer (65), the second layer (55), the base layer (4) to the drift layer (3).

Abstract translation: 提供一种功率半导体器件（1），其包括以下顺序： - 集电极（1）， - 第二导电类型的集电极层（2）， - 第一导电类型的漂移层（3） - 第二导电类型的基极层（4）， - 具有开口（82）的第一绝缘层（8）， - 第一导电类型的发射极层（5），其中发射极层（5）处于 与基底层（4）接触并且至少由第一绝缘层（8）或基底层（4）中的一个与漂移层（3）分离， - 布置成第二导电类型的体层（6） 横向到发射极层（5）并且通过第一绝缘层（8）和发射极层（5）与基极层（4）分离， - 与发射极层分离的第一导电类型的源极区域（7） （5）通过所述主体层（6）， - 与所述源极区域（7）接触的发射极（15）。 该装置还包括与发射电极（15）接触并与基底层（4）分离的第二导电类型的第一层（65）和第一导电类型的第二层（55），其布置在第一 层（65）和基底层（4），并与发射极层（5）和源极区域（7）分离。 平面的MIS栅电极（9）从发射电极（15）侧向设置，相应的MIS通道可在源极区（7），主体层（6）和发射极层（5）之间形成。 晶闸管电流路径（120）通过开口（82）在发射极层（5），基极层（4）和漂移层（3）之间延伸，并且关断MIS通道（110）可形成在 从第一层（65），第二层（55），基底层（4）到漂移层（3）的平面MIS栅电极（9）。

公开(公告)号：WO2014140094A1

公开(公告)日：2014-09-18

申请号：PCT/EP2014/054830

申请日：2014-03-12

Applicant: ABB TECHNOLOGY AG

Inventor： RAHIMO, Munaf

IPC: H01L29/745 ,  H01L29/749 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7395 ,  H01L27/0623 ,  H01L29/0696 ,  H01L29/0813 ,  H01L29/0821 ,  H01L29/083 ,  H01L29/1004 ,  H01L29/1012 ,  H01L29/1016 ,  H01L29/102 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/7455 ,  H01L29/749

Abstract: A power semiconductor device (1) of the emitter switched thyristor (EST) type comprising an emitter electrode (2) and a collector electrode (25) on opposite sides (22, 27) of a wafer (10), wherein a gate electrode (7) arranged on the emitter side (22) comprises a conductive gate layer (72) and an insulating layer (74), wherein layers are arranged in the following order between the collector and emitter sides (27, 22): a p doped collector layer (6), an n- doped drift layer (5), an n doped enhancement layer (52), a p doped base layer (4) with first and second base regions (42, 44), and n+ doped first and second emitter layers (3, 35), wherein the emitter electrode (2) contacts the first emitter layer (3) and the first base region (42), wherein the second emitter layer (35) is insulated from the emitter electrode (2) by the insulating layer (74) and wherein the second emitter layer (35) is separated from the first emitter layer (3) by the base layer (4), wherein the enhancement layer (52) is arranged between the first base region (42) and the drift layer (5), separates the first base region (42) from the second base region (44) and the drift layer (5) and contacts the second emitter layer (35), wherein an IGBT channel (100) is formable from the first emitter layer (3) via the first base region (42) to the drift layer (5), wherein a thyristor channel (120) is formable from the second emitter layer (35) via the second base region (44) to the drift layer (5), wherein a MOS channel (140) is formable from first emitter layer (3) via the first base region (42) to the second emitter layer (35).

Abstract translation: 发射极开关晶闸管（EST）型的功率半导体器件（1）包括在晶片（10）的相对侧（22,27）上的发射极（2）和集电极（25），其中栅电极 配置在发射极侧（22）上的电荷层（7,7）包括导电栅极层（72）和绝缘层（74），其中层在集电极和发射极侧（27,22）之间按照以下顺序排列： （6），n掺杂漂移层（5），n掺杂增强层（52），具有第一和第二基极区（42,44）的p掺杂基底层（4），以及n +掺杂的第一和第二发射极层 （3,35），其中所述发射电极（2）接触所述第一发射极层（3）和所述第一基极区域（42），其中所述第二发射极层（35）通过绝缘体与所述发射极（2）绝缘 层（74），并且其中所述第二发射极层（35）由所述基底层（4）与所述第一发射极层（3）分离，其中所述增强层（52） 布置在第一基极区域（42）和漂移层（5）之间，将第一基极区域（42）与第二基极区域（44）和漂移层（5）分离并接触第二发射极层（35） ，其中IGBT通道（100）可以通过第一基极区（42）从第一发射极层（3）形成到漂移层（5），其中晶闸管通道（120）可从第二发射极层（35）形成 ）经由第二基极区（44）到漂移层（5），其中MOS沟道（140）可以经由第一基极区（42）从第一发射极层（3）形成到第二发射极层（35）。

公开(公告)号：WO2007135694A8

公开(公告)日：2008-12-31

申请号：PCT/IT2006000372

申请日：2006-05-18

Applicant: ST MICROELECTRONICS SRL ,  RONSISVALLE CESARE ,  ENEA VINCENZO

Inventor： RONSISVALLE CESARE ,  ENEA VINCENZO

IPC: H01L29/745 ,  H01L29/74 ,  H01L29/749

CPC classification number: H01L29/7395 ,  H01L29/742 ,  H01L29/7455

Abstract: Described herein is a power device (10) having a first current-conduction terminal (A) , a second current-conduction terminal (K) , a control terminal (G) receiving, in use, a control voltage (VGATE) of the power device (10), and a thyristor device (12) and a first insulated-gate switch device (14) connected in series between the first and the second conduction terminals; the first insulated-gate switch device (14) has a gate terminal connected to the control terminal (G), and the thyristor device (12) has a base terminal (16) . The power device (10) is further provided with: a second insulated-gate switch device (18), connected between the first current-conduction terminal (A) and the base terminal (16) of the thyristor device (12) , and having a respective gate terminal connected to the control terminal (G) ; and a Zener diode (19) , connected between the base terminal (16) of the thyristor device (12) and the second current-conduction terminal (K) so as to enable extraction of current from the base terminal (16) in a given operating condition.

Abstract translation: 这里描述的是具有第一通电端子（A），第二通电端子（K），控制端子（G）的功率器件（10），其在使用中接收功率的控制电压（VGATE） 装置（10）和串联连接在第一和第二导电端子之间的晶闸管装置（12）和第一绝缘栅极开关装置（14） 第一绝缘栅极开关器件（14）具有连接到控制端子（G）的栅极端子，并且晶闸管器件（12）具有基极端子（16）。 功率器件（10）还具有连接在晶闸管器件（12）的第一通电端子（A）和基极端子（16）之间的第二绝缘栅极开关器件（18），并具有 连接到所述控制端子（G）的相应的栅极端子; 和连接在晶闸管器件（12）的基极端子（16）和第二通电端子（K）之间的齐纳二极管（19），以便能够在给定的基极端子（16）中提取电流 操作条件。

公开(公告)号：WO02037569A2

公开(公告)日：2002-05-10

申请号：PCT/US2001/031840

申请日：2001-10-11

IPC: H01L29/749 ,  H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78 ,  H01L29/00

CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/749 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A trench MOS-gated device (200) comprises a doped monocrystalline semiconductor substrate (201) that includes an upper layer (201a) and is of a first conductivity type. An extended trench (202) in the substrate in the upper layer comprises two segments (203,204) having differing widths relative to one another: a bottom segment (204) of lesser width filled with a dielectric material (209), and an upper (203) segment of greater width lined with a dielectric material (205,206) and substantially filled with a conductive material (207), the filled upper segment of the trench forming a gate region (208). An extended doped zone (215) of a second opposite conductivity type extends from an upper surface (212) into the upper layer (210a) of the substrate only on one side of the trench (202), and a doped well region (210) of the second conductivity type overlying a drain zone (211) of the first conductivity type is disposed in the upper layer (201a) on the opposite side of the trench.

Abstract translation: 沟槽MOS门控器件（200）包括掺杂单晶半导体衬底（201），其包括上层（201a）并且是第一导电类型。 在上层中的衬底中的延伸沟槽（202）包括相对于彼此具有不同宽度的两个段（203,204）：填充有介电材料（209）的较小宽度的底部段（204）和上部（203 ）段，其具有用电介质材料（205,206）内衬并且基本上填充有导电材料（207）的较大宽度，所述沟槽的填充的上部段形成栅极区域（208）。 第二相反导电类型的扩展掺杂区域（215）仅在沟槽（202）的一侧从上表面（212）延伸到衬底的上层（210a）中，并且掺杂阱区域（210） 覆盖在第一导电类型的漏区（211）上的第二导电类型的第二导电类型设置在沟槽相对侧上的上层（201a）中。

公开(公告)号：WO01086728A1

公开(公告)日：2001-11-15

申请号：PCT/FR2001/001402

申请日：2001-05-09

IPC: H01L29/749 ,  H01L27/04 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78

CPC classification number: H01L29/7392 ,  H01L29/7455

Abstract: The invention concerns an anode voltage sensor of a vertical power component selected from the group consisting of components called thyristor, MOS, IGBT, PMCT, EST, BRT transistor, MOS thyristor, turn-off MOS thyristor, formed by a lightly doped N-type substrate (1) whereof the rear surface (2) having a metallizing coat corresponds to the component anode. Said sensor comprises, on the front surface side, a substrate zone (12) surrounded at least partly by a P-type region with low potential in front of an anode potential, said zone (12) being coated with a metallizing coat (M) in ohmic contact with it, whereon is provided an image of the anode voltage.

Abstract translation: 本发明涉及一种垂直功率元件的阳极电压传感器，其选自由轻掺杂N型形成的组件，称为晶闸管，MOS，IGBT，PMCT，EST，BRT晶体管，MOS晶闸管，截止MOS晶闸管 具有金属化涂层的背面（2）的基板（1）对应于部件阳极。 所述传感器在前表面侧包括至少部分地由阳极电位前面具有低电位的P型区域包围的衬底区域（12），所述区域（12）涂覆有金属化涂层（M） 与其进行欧姆接触，其中提供了阳极电压的图像。

公开(公告)号：WO00068474A1

公开(公告)日：2000-11-16

申请号：PCT/JP2000/002932

申请日：2000-05-08

IPC: H01L29/74 ,  C30B25/20 ,  C30B29/36 ,  H01L21/04 ,  H01L21/205 ,  H01L21/28 ,  H01L29/04 ,  H01L29/24 ,  H01L29/47 ,  H01L29/749 ,  H01L29/78 ,  H01L29/861 ,  H01L29/872 ,  H01L21/20

CPC classification number: H01L29/1608 ,  H01L21/0445 ,  H01L29/045

Abstract: An SiC substrate (2) having a plane orientation of almost (11-20) and being of a 4H type polytype or 15R type polytype, and a buffer layer (4) formed on the SiC substrate (2) and made of SiC are provided.

Abstract translation: 提供具有几乎（11-20）的平面取向并且是4H型多型或15R型多型的SiC衬底（2）和形成在SiC衬底（2）上并由SiC制成的缓冲层（4） 。

公开(公告)号：WO9933119A3

公开(公告)日：1999-08-26

申请号：PCT/IB9802027

申请日：1998-12-14

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PHILIPS SVENSKA AB

Inventor： CUTTER JOHN ROGER

IPC: H01L29/749 ,  H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/6634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7396 ,  H01L29/7802

Abstract: A power semiconductor device comprises a multiple-cellular insulated-gate field-effect transistor structure with each cell (100) present at a corresponding opening (110) in a mesh-shaped gate electrode (11). The cells (100) and the openings (110) are of elongate shape having longitudinal sides (X) at which the channel areas (1) are present under a gate insulating layer (12) under longitudinal parts (11x) of the gate electrode (11). The channel areas (1) are absent at ends (Z) of the elongate cells (100). Preferably, the longitudinal parts (11x) of the gate electrode (11) are interconnected beyond the ends (Z) of the elongate cells (100) by interconnection parts (11z) of the gate electrode (11) which are located on a thicker insulating layer (13) than the gate insulating layer (12). This thicker insulating layer (13) is present at least between facing ends (Z) of neigbouring elongate cells (100) where the channel areas (11) are absent.

Abstract translation: 功率半导体器件包括多单元绝缘栅场效应晶体管结构，每个单元（100）存在于网状栅电极（11）中的对应开口（110）处。 电池（100）和开口（110）具有细长形状，具有纵向侧面（X），沟槽区域（1）在栅极绝缘层（12）的下方位于栅极电极的纵向部分（11x）下方 11）。 在细长细胞（100）的端部（Z）处不存在通道区域（1）。 优选地，栅电极（11）的纵向部分（11x）通过栅电极（11）的互连部分（11z）互连在细长电池（100）的端部（Z）之间，该部分位于较厚的绝缘体 （13）比栅绝缘层（12）。 该较厚的绝缘层（13）至少存在于不存在通道区域（11）的邻近细长单元（100）的相对端（Z）之间。

公开(公告)号：WO9736316A3

公开(公告)日：1997-11-20

申请号：PCT/SE9700451

申请日：1997-03-18

Applicant: ABB RESEARCH LTD ,  HARRIS CHRISTOPHER ,  BAKOWSKI MIETEK ,  GUSTAFSSON ULF ,  ANDERSSON MATS

Inventor： HARRIS CHRISTOPHER ,  BAKOWSKI MIETEK ,  GUSTAFSSON ULF ,  ANDERSSON MATS

IPC: H01L21/04 ,  H01L29/24 ,  H01L29/739 ,  H01L29/745 ,  H01L29/749 ,  H01L

CPC classification number: H01L29/1608 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7455 ,  H01L29/749

Abstract: A field controlled semiconductor device of SiC comprising superimposed in the order mentioned a drain (15), a highly doped substrate layer (1), a highly doped n-type buffer layer (2) and a low doped n-type drift layer (3). It also has a highly doped n-type source region layer (7) and a source (14) connected thereto, a vertical trench (9) from above, a low doped n-type channel region layer (6) extending vertically along a wall (11) of said trench and connecting said source region layer to said drift layer and through which a current is intended to flow when the device is in an on-state. A gate electrode (12) is arranged in said trench at least along said wall and to, upon applying a voltage thereto, influence the charge carrier distribution of said channel region layer and by that the conductivity thereof. The device comprises further a p-type base layer (4) arranged laterally next to said channel region layer at the opposite side thereof with respect to the gate electrode for forming a vertical conducting channel in said channel region layer at a distance from said trench wall.

公开(公告)号：WO2021251764A1

公开(公告)日：2021-12-16

申请号：PCT/KR2021/007261

申请日：2021-06-10

Applicant: 한국전자통신연구원

Inventor： 박건식 ,  원종일 ,  조두형 ,  정동윤 ,  장현규

IPC: H01L29/749 ,  H01L29/745 ,  H01L29/66 ,  H01L29/10

Abstract: 본 발명의 개념에 따른 모스 구동 사이리스터 소자는 마주하는 제1 면 및 제2 면을 포함하는 기판, 상기 제1 면 상에 배치되는 게이트 패턴들, 상기 게이트 패턴들을 덮는 캐소드 전극, 및 상기 제2 면 상에 배치되는 애노드 전극을 포함한다. 상기 기판은 제1 도전형을 가지는 하부 에미터 층, 상기 하부 에미터 층 상에 제2 도전형을 가지는 하부 베이스 층, 상기 하부 베이스 층의 상부에 제공되고, 제1 도전형을 가지는 상부 베이스 영역, 상기 상부 베이스 영역은 상기 하부 베이스 층의 상면 일부를 노출시키고, 상기 상부 베이스 영역의 상부에 제공되는 제2 도전형을 가지는 상부 에미터 영역, 상기 상부 에미터 영역의 상부에 제공되고, 제1 도전형을 가지는 제1 도핑 영역 및 상기 제1 도핑 영역으로부터 둘러싸이는 제2 도전형을 가지는 제2 도핑 영역, 및 상기 상부 에미터 영역의 상부의 일측면에 제공되는 제1 도전형을 가지는 제1 도핑 패턴을 포함한다.상기 제1 도핑 패턴은 기판의 상면에 평행한 제1 방향을 따라서 상기 상부 베이스 영역 및 상기 제1 도핑 영역 사이에 개재된다. 상기 제1 도핑 패턴은 상기 상부 에미터 영역의 상부의 타 측면에서 상기 상부 에미터 영역의 상면을 노출시킨다. 상기 게이트 패턴들의 각각은 상기 노출된 하부 베이스 층의 상면, 상기 노출된 상부 베이스 영역의 상면, 상기 노출된 상부 에미터 영역의 상면, 상기 제1 도핑 패턴, 및 상기 제1 도핑 영역의 일부를 덮는다. 상기 캐소드 전극은 상기 게이트 패턴의 상면 및 측면, 상기 제2 도핑 영역의 상면과 상기 제1 도핑 영역의 상면의 일부를 덮는다. 상기 제1 도전형과 상기 제2 도전형은 서로 다르다.

公开(公告)号：WO2021194932A1

公开(公告)日：2021-09-30

申请号：PCT/US2021/023413

申请日：2021-03-22

Applicant: LITTELFUSE, INC.

Inventor： YOSHIMOTO, Koichiro

IPC: H01L29/74 ,  H01L29/744 ,  H01L29/745 ,  H01L29/747 ,  H01L29/749 ,  H01L23/49562 ,  H01L23/49575 ,  H01L29/66386 ,  H03K17/60

Abstract: A power control switch assembly. The assembly may include a thyristor device, where the thyristor device includes a first device terminal, a second device terminal, and a gate terminal> The assembly may include a negative temperature coefficient (NTC) device, electrically coupled to the gate terminal of the thyristor device on a first end, and electrically coupled to the first device terminal of the thyristor device on a second end, wherein the NTC device is thermally coupled to the thyristor device.