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    REVERSE CONCATENATION OF ERROR-CORRECTING CODES IN DNA DATA STORAGE
    2.
    发明申请
    REVERSE CONCATENATION OF ERROR-CORRECTING CODES IN DNA DATA STORAGE 审中-公开

    公开(公告)号：WO2021045816A1

    公开(公告)日：2021-03-11

    申请号：PCT/US2020/037995

    申请日：2020-06-17

    Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC

    Inventor： YEKHANIN, Sergey ,  GOPI, Sivakanth ,  PFISTER, Henry ,  STRAUSS, Karin

    IPC: G16B50/00 ,  G11C13/02

    Abstract: Redundancy information can be included in nucleotide symbol strings encoding underlying data. To avoid propagation of errors during the decoding process, during encoding, a constrained encoding can be performed before the redundancy information is computed. The redundancy information can be an outer encoding across multiple nucleotide symbol strings. An inner coding within nucleotide symbol strings can also be supported. Such redundancy information can be interleaved into the underlying nucleotide symbol strings to which the constrained encoding has been applied, resulting in a relaxed constraint. Insertion/deletion redundancy information can also be included in the resulting strings, and an insertion/deletion-sensitive sequence can be included to assist in recovering accurate sequences during decoding operations.

    記憶セル、記憶回路、及び記憶方法
    3.
    发明申请
    記憶セル、記憶回路、及び記憶方法 审中-公开
    存储单元，存储电路和存储方法

    公开(公告)号：WO2016186148A1

    公开(公告)日：2016-11-24

    申请号：PCT/JP2016/064798

    申请日：2016-05-18

    Applicant: 国立大学法人東北大学

    Inventor： 一杉　太郎 ,  白木　将 ,  鈴木　竜

    IPC: H01L27/10 ,  G11C13/00 ,  G11C13/02 ,  H01L27/105

    CPC classification number: G11C13/00 ,  G11C13/02 ,  H01L27/10 ,  H01L27/105

    Abstract: 記憶セル（１１）は、正極（２２）と正極（２２）上に形成された電解質層と電解質層上に形成された負極（２４）とから構成される。電解質層は、例えば、正極（２２）と反応して化合物を生成する物質を含む。電解質層は、例えば、負極（２４）に含まれる物質と同一で、正極（２２）と反応して化合物を生成する物質を含む。記憶セル（１１）は、例えば、正極（２２）から電解質層を通って負極（２４）に向かう電流の供給により、化合物が分解され、負極（２４）から電解質層を通って正極（２２）に向かう電流の供給により、化合物が生成される。

    Abstract translation: 该蓄电单元（11）由正极（22），形成在正极（22）上的电解质层和形成在电解质层上的负极（24）构成。 电解质层包含例如通过与正极（22）反应而产生化合物的物质。 电解质层含有例如与负极（24）中所含的物质相同的物质，并且通过与正极（22）反应而产生化合物。 对于该蓄电池（11），例如，通过从电解质层向正极（22）向负极（24）供给电流而分解化合物，通过供给来制造化合物 通过电解质层从负极（24）流向正极（22）的电流。

    INTEGRATED SYSTEM FOR NUCLEIC ACID-BASED STORAGE OF DIGITAL DATA
    4.
    发明申请
    INTEGRATED SYSTEM FOR NUCLEIC ACID-BASED STORAGE OF DIGITAL DATA 审中-公开
    用于基于核酸的数字数据存储的集成系统

    公开(公告)号：WO2016164779A1

    公开(公告)日：2016-10-13

    申请号：PCT/US2016/026726

    申请日：2016-04-08

    Applicant: UNIVERSITY OF WASHINGTON

    Inventor： CEZE, Luis, Henrique ,  SEELIG, Georg

    IPC: G06N3/12 ,  G06F17/30 ,  G06F19/22 ,  G11C13/02

    CPC classification number: G06F19/22 ,  G06F17/30 ,  G06F19/20 ,  G06F19/28 ,  G06N3/12 ,  G11C13/0019 ,  G11C13/02

    Abstract: In some embodiments, systems and methods for storing and/or retrieving digital information in a nucleic acid library are provided. In some embodiments, an integrated system comprising a nucleic acid synthesis device, a nucleic acid sequencing device, a computing device, and a nucleic acid library is provided. In some embodiments, a write request that associates a value with a key is received by the system, the system synthesizes nucleic acid molecules associated with the request, and stores the nucleic acid molecules in the nucleic acid library. In some embodiments, a read request for a key is received by the system, and the system sequences nucleic acid molecules from the nucleic acid library that are associated with the key.

    Abstract translation: 在一些实施例中，提供了用于在核酸库中存储和/或检索数字信息的系统和方法。 在一些实施方案中，提供了包含核酸合成装置，核酸测序装置，计算装置和核酸文库的整合系统。 在一些实施例中，将值与密钥相关联的写请求由系统接收，系统合成与请求相关联的核酸分子，并将核酸分子存储在核酸文库中。 在一些实施例中，系统接收到对密钥的读取请求，并且系统从与该密钥相关联的核酸库序列核酸分子。

    MEMORY ARRAYS AND METHODS OF FORMING MEMORY ARRAYS
    7.
    发明申请
    MEMORY ARRAYS AND METHODS OF FORMING MEMORY ARRAYS 审中-公开
    记忆阵列和形成记忆阵列的方法

    公开(公告)号：WO2015147940A1

    公开(公告)日：2015-10-01

    申请号：PCT/US2014/072584

    申请日：2014-12-29

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： BONIARDI, Mattia ,  REDAELLI, Andrea

    IPC: G11C13/02 ,  G11C5/02

    CPC classification number: H01L45/1293 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/128 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1675

    Abstract: Some embodiments include memory arrays having a plurality of memory cells vertically between bitlines and wordlines. The memory cells contain phase change material. Heat shields are laterally between immediately adjacent memory cells along a bitline direction. The heat shields contain electrically conductive material and are electrically connected with the bitlines. Some embodiments include memory arrays having a plurality of memory cells arranged in a first grid. The first grid has columns along a first direction and has rows along a second direction substantially orthogonal to the first direction. First heat shields are between adjacent memory cells along the first direction and are arranged in a second grid offset from the first grid along the first direction. Second heat shields are between adjacent memory cells along the second direction, and are arranged lines in lines extending along the first direction. Some embodiments include methods for forming memory arrays.

    Abstract translation: 一些实施例包括在位线和字线之间垂直地具有多个存储单元的存储器阵列。 存储单元包含相变材料。 热屏蔽沿着位线方向横向位于紧邻的存储单元之间。 隔热罩包含导电材料并与位线电连接。 一些实施例包括具有布置在第一网格中的多个存储单元的存储器阵列。 第一格栅具有沿着第一方向的列，并且沿着与第一方向大致正交的第二方向具有列。 第一热屏蔽沿着第一方向位于相邻存储单元之间，并且沿着第一方向布置成与第一格栅偏移的第二格栅。 第二隔热板沿着第二方向位于相邻存储单元之间，并沿着第一方向延伸的线排列。 一些实施例包括用于形成存储器阵列的方法。

    PHASE CHANGE MEMORY WITH SWITCH (PCMS) WRITE ERROR DETECTION
    10.
    发明申请
    PHASE CHANGE MEMORY WITH SWITCH (PCMS) WRITE ERROR DETECTION 审中-公开
    相位变化记忆与开关（PCMS）写入错误检测

    公开(公告)号：WO2013101196A1

    公开(公告)日：2013-07-04

    申请号：PCT/US2011/068139

    申请日：2011-12-30

    Applicant: INTEL CORPORATION ,  QAWAMI, Shekoufeh ,  SUNDARAM, Rajesh

    Inventor： QAWAMI, Shekoufeh ,  SUNDARAM, Rajesh

    IPC: G11C29/00 ,  G11C13/02 ,  G06F11/16

    CPC classification number: G06F11/1048 ,  G06F11/073 ,  G06F11/0763 ,  G06F11/1068 ,  G11C13/0004

    Abstract: Methods and apparatus related to PCMS (Phase Change Memory with Switch) write error detection are described. In one embodiment, a first storage unit stores a single bit to indicate whether an error corresponding to a write operation in any of one or more PCMS devices has occurred. Also, one or more storage units each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCMS devices. Other embodiments are also disclosed and claimed.

    Abstract translation: 描述了与PCMS（带切换的相变存储器）写入错误检测相关的方法和装置。 在一个实施例中，第一存储单元存储单个位以指示是否发生了与一个或多个PCMS设备中的任一个中的写入操作相对应的错误。 此外，一个或多个存储单元每个存储多个位以指示与一个或多个PCMS设备的多个分区的分区中是否发生了与写入操作相对应的错误。 还公开并要求保护其他实施例。

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