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    SURFACE PLANARISATION
    3.
    发明申请
    SURFACE PLANARISATION 审中-公开
    表面平面图

    公开(公告)号：WO2012131288A1

    公开(公告)日：2012-10-04

    申请号：PCT/GB2012/000259

    申请日：2012-03-21

    Applicant: CAMBRIDGE DISPLAY TECHNOLOGY LIMITED ,  FLEISSNER, Arne ,  MALIK, Surama ,  BAKER, Colin ,  SCULLION, Laurence ,  BURROUGHES, Jeremy

    Inventor： FLEISSNER, Arne ,  MALIK, Surama ,  BAKER, Colin ,  SCULLION, Laurence ,  BURROUGHES, Jeremy

    IPC: G03F7/20 ,  H01L51/00 ,  B05D5/08 ,  H01L21/768

    CPC classification number: H01L21/306 ,  G03F7/2022 ,  H01L29/02 ,  H01L51/0001 ,  H01L51/0003 ,  H01L51/0018 ,  H01L51/0096 ,  H01L51/5212 ,  H01L2251/5361 ,  H01L2251/5392 ,  Y02E10/549

    Abstract: This invention generally relates to planarisation of a surface of a substrate. In an embodiment of planarising a surface region of a substrate, the substrate having a body on a portion of said surface region, the method comprises: modifying the wetability of a surface of said body with respect to a liquid planariser composition by providing a surface modifying layer such as a self-assembled monolayer thereon; and then depositing the liquid planariser composition on said substrate and said body such that the planariser composition wets said surface region, wherein said surface modifying layer determines a contact angle of said liquid planariser composition to said surface of said body such that the deposited liquid planariser composition is repelled from said surface of said body.

    Abstract translation: 本发明一般涉及基板表面的平面化。 在平面化衬底的表面区域的一个实施例中，衬底在所述表面区域的一部分上具有主体，该方法包括：通过提供表面修饰来改变所述主体的表面相对于液体平面剂组合物的可润湿性 层，例如其上的自组装单层; 然后将液体平面剂组合物沉积在所述基材和所述体上，使得平面剂组合物润湿所述表面区域，其中所述表面改性层确定所述液体平面剂组合物与所述体的所述表面的接触角，使得沉积的液体平面剂组合物 从所述身体的所述表面排出。

    HETEROSTRUCTURE SPHERICAL SHAPED SEMICONDUCTOR DEVICE
    4.
    发明申请
    HETEROSTRUCTURE SPHERICAL SHAPED SEMICONDUCTOR DEVICE 审中-公开
    异质结构球形半导体器件

    公开(公告)号：WO00062349A1

    公开(公告)日：2000-10-19

    申请号：PCT/US2000/007393

    申请日：2000-03-20

    IPC: H01L21/20 ,  H01L21/205 ,  H01L29/02 ,  H01L31/072 ,  H01L21/331 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/109

    CPC classification number: H01L21/02381 ,  H01L21/0243 ,  H01L21/02546 ,  H01L29/02

    Abstract: A method and apparatus for heteroepitaxially growing an epi layer on a spherical shaped single-crystal semiconductor substrate is disclosed. The method grows a first portion of the epi layer on a first offset portion of the spherical shaped single-crystal semiconductor substrate in which the lattice constant of the growth layer equals the lattice constant of the offset portion. The epi layer is further grown laterally, covering additional portions of the substrate.

    Abstract translation: 公开了一种在球形单晶半导体衬底上异质外延生长外延层的方法和装置。 该方法在球形单晶半导体衬底的第一偏移部分上生长外延层的第一部分，其中生长层的晶格常数等于偏移部分的晶格常数。 外延层进一步横向生长，覆盖基底的另外部分。

    电致发光器件及其制造方法、显示基板和显示装置
    5.
    发明申请
    电致发光器件及其制造方法、显示基板和显示装置 审中-公开

    公开(公告)号：WO2016045272A1

    公开(公告)日：2016-03-31

    申请号：PCT/CN2015/071098

    申请日：2015-01-20

    Applicant: 京东方科技集团股份有限公司

    Inventor： 井口真介 ,  廖金龙 ,  高雪

    IPC: H01L29/02 ,  H01L33/00

    CPC classification number: H01L29/02 ,  H01L33/00

    Abstract: 一种电致发光器件及其制造方法、显示基板和显示装置，该电致发光器件包括：基板（1）和形成于基板（1）的上方的像素界定层（2），像素界定层（2）上形成有像素开口矩阵，该像素开口矩阵包括多个像素开口（3），像素开口（3）内形成有电致发光层（4），处于同一列的全部电致发光层中至少存在一个电致发光层与其他电致发光层的厚度不相等。通过将电致发光器件内的处于同一列的全部电致发光层中的至少一个电致发光层设置为与其他电致发光层的厚度不相等，从而使得对应列中的电致发光层在发光时所产生的亮度不均匀，进而使得电致发光器件上的条纹mura被淡化，提升了该电致发光器件的品质。

    TRANSISTOR STRUCTURES AND METHODS FOR MAKING THE SAME
    9.
    发明申请
    TRANSISTOR STRUCTURES AND METHODS FOR MAKING THE SAME 审中-公开
    晶体管结构及其制造方法

    公开(公告)号：WO2004038757A2

    公开(公告)日：2004-05-06

    申请号：PCT/US2003/015527

    申请日：2003-05-15

    Applicant: THE STATE OF OREGON acting by and through THE STATE BOARD OF HIGHER EDUCATION on behalf of OREGON STATE UNIVERSITY ,  WAGER, John, F., III ,  HOFFMAN, Randy, L.

    Inventor： WAGER, John, F., III ,  HOFFMAN, Randy, L.

    IPC: H01L

    CPC classification number: H01L29/02 ,  H01L29/45 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78681 ,  H01L29/7869

    Abstract: Enhancement mode, field effect transistors wherein at least a portion of the transistor structure may be substantially transparent. One variant of the transistor includes a channel layer comprising a substantially insulating, substantially transparent, material selected from ZnO, Sn0 2 , or In 2 0 3 . A gate insulator layer comprising a substantially transparent material is located adjacent to the channel layer so as to define a channel layer/gate insulator layer interface. A second variant of the transistor includes a channel layer comprising a substantially transparent material selected from substantially insulating ZnO, Sn0 2 or In 2 O 3 , the substantially insulating ZnO, Sn0 2 , or In 2 0 3 being produced by annealing. Devices that include the transistors and methods for making the transistors are also disclosed.

    Abstract translation: 增强模式，场效应晶体管，其中晶体管结构的至少一部分可以是基本透明的。 晶体管的一个变体包括沟道层，该沟道层包括选自ZnO，SnO 2或In 2 O 3： >。 包括基本透明材料的栅极绝缘体层位于沟道层附近，以便限定沟道层/栅极绝缘体层界面。 晶体管的第二变体包括沟道层，该沟道层包括从基本绝缘的ZnO，SnO 2或In 2 O 3中选择的基本上透明的材料， 基本绝缘的ZnO，SnO 2或In 2 O 3通过退火产生。 还公开了包括晶体管的器件和制造晶体管的方法。

    HIGH-RESISTIVITY SILICON CARBIDE SUBSTRATE FOR SEMICONDUCTOR DEVICES WITH HIGH BREAKDOWN VOLTAGE
    10.
    发明申请
    HIGH-RESISTIVITY SILICON CARBIDE SUBSTRATE FOR SEMICONDUCTOR DEVICES WITH HIGH BREAKDOWN VOLTAGE 审中-公开
    具有高突变电压的半导体器件的高电阻碳化硅衬底

    公开(公告)号：WO2002092886A1

    公开(公告)日：2002-11-21

    申请号：PCT/US2002/014430

    申请日：2002-05-08

    Applicant: CREE INC. ,  MUELLER, Stephan

    Inventor： MUELLER, Stephan

    IPC: C30B29/36

    CPC classification number: H01L29/1608 ,  C30B23/00 ,  C30B25/00 ,  C30B29/36 ,  H01L21/0445 ,  H01L29/02

    Abstract: A high-resistivity silicon carbide single crystal is disclosed that includes at least one compensated dopant having an electronic energy level far enough from an edge of the silicon carbide bandgap to avoid conductive behavior, while far enough from mid-gap towards the band edge to create a greater band offset than do mid-level states when the substrate is in contact with a doped silicon carbide epitaxial layer and when the net amount of the dopant present in the crystal is sufficient to pin the Fermi level at the dopant's electronic energy level. The silicon carbide crystal has a restivity of at least 5000 ohms-centimeters at room temperature.

    Abstract translation: 公开了一种高电阻率碳化硅单晶，其包括至少一种补偿的掺杂剂，其具有距碳化硅带隙边缘足够远的电子能级，以避免导电性能，同时从中间隙朝向带边缘足够远以产生 当衬底与掺杂的碳化硅外延层接触时，当晶体中存在的掺杂剂的净量足以在掺杂剂的电子能级引导费米能级时，具有比中级状态更大的带偏移。 碳化硅晶体在室温下具有至少5000欧姆 - 厘米的复制度。

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