US09509476B2
Disclosed are a method and a device for detecting control signalling and implementing control signalling detection. In a subframe S, a terminal detects the control signalling in K ePDCCH resource sets; the terminal detects set X(i) of aggregation level of the resource in Set i of the K ePDCCH resource sets, wherein i is an integer, 0
US09509471B2
The present invention relates to a wireless communication system. A method for transmitting channel state information (CSI) by a user equipment in a wireless communication system includes receiving a CSI-reference signal (CSI-RS), determining overhead of a common reference signal (CRS) resource element based on the same antenna port number as an antenna port number associated with the CSI-RS, and transmitting the CSI calculated based on the CSI-RS and the overhead of the CRS resource element.
US09509468B2
In one embodiment, a method in a network node is provided. The network node is configured to use a first power level for transmitting data in subframes of a first type, and to use a second power level for transmitting data in subframes of a second type. The method comprises signaling (520) first and second information to a network entity. From the first information, a power offset for subframes of the first type is derivable. The first power offset represents a relation between a power level for transmitting reference signals and the first power level. From the second information, a power offset for subframes of the second type is derivable. The second power offset represents a relation between the power level for transmitting reference signals, and the second power level.
US09509465B2
Embodiments of a very-high throughput communication station and method for communicating on a primary channel and up to three or more secondary channels are generally described herein. Short-preamble detection may be performed during a contention window to detect packet transmissions on any one of the secondary channels starting within the contention window. Guard-interval detection is also performed during the contention window to detect a guard interval of a packet transmission on any one of the secondary channels. The short-preamble detection and the guard-interval detection may be performed concurrently during the contention window to determine if any of the secondary channels are busy.
US09509462B2
The present invention is designed to, upon updating CQIs that are fed back, prevent the increase of the overhead of feedback information, and still improve the accuracy of the updated CQIs when CoMP transmission is applied. The radio communication system of the present invention is formed with a plurality of radio base station apparatuses and a user terminal that is configured to be able to perform coordinated multiple point transmission/reception with the plurality of radio base station apparatuses, and the user terminal acquires channel state information of multiple cells, generates feedback information such that the channel state information of multiple cells is allotted and transmitted in a plurality of subframes, and feeds back the generated feedback information to the radio base station apparatus of one of the multiple coordinated points, using a physical uplink shared data channel.
US09509459B2
Methods and apparatus are described for mitigating intercell interference in wireless communication systems utilizing substantially the same operating frequency band across multiple neighboring coverage areas. The operating frequency band may be shared across multiple neighboring or otherwise adjacent cells, such as in a frequency reuse one configuration. The wireless communication system can synchronize one or more resource allocation regions or zones across the multiple base stations, and can coordinate a permutation type within each resource allocation zone. The base stations can coordinate a pilot configuration in each of a plurality of coordinated resource allocation regions. Subscriber stations can be assigned resources in a coordinated resource allocation region based on interference levels. A subscriber station can determine a channel estimate for each of multiple base stations in the coordinated resource allocation region to mitigate interference.
US09509456B2
A transmitter and a receiver for transmitting and receiving data via a power supply line comprise a local signal port for respectively receiving and transmitting a serial bit stream and a power line connection port for respectively transmitting a radio frequency signal and receiving the radio frequency signal via the power supply line. The transmitter comprises a modulator unit adapted for encoding the serial bit stream into a baseband signal and generating the radio frequency signal by mixing the baseband signal with a carrier wave so as to redundantly convey the at least one baseband signal in at least four spectral sidebands of the carrier wave. The receiver comprises a demodulator unit adapted for detecting the at least four spectral sidebands of the carrier wave in the radio frequency signal, isolating a baseband signal from the at least four spectral sidebands and decoding the baseband signal into the serial bit stream.
US09509452B2
Techniques to increase the capacity of a W-CDMA wireless communications system. In an exemplary embodiment, early termination of one or more transport channels on a W-CDMA wireless communications link is provided. In particular, early decoding is performed on slots as they are received over the air, and techniques are described for signaling acknowledgment messages (ACK's) for one or more transport channels correctly decoded to terminate the transmission of those transport channels. The techniques may be applied to the transmission of voice signals using the adaptive multi-rate (AMR) codec. Further exemplary embodiments describe aspects to reduce the transmission power and rate of power control commands sent over the air, as well as aspects for applying tail-biting convolutional codes in the system.
US09509447B2
A method of performing a Network Coding (NC) by a transmitting node in a wireless communication system, the method comprising receiving uplink packets from a plurality of nodes through respective links, grouping the links into at least one group based on channel quality information, each group satisfying a listed range of channel quality information, performing the NC on downlink data for each group and transmitting each scheduling information shared by each group to the at least one respective group. A method of receiving network-coded data in a wireless communication system comprises transmitting an uplink packet to a transmitting node, receiving scheduling information shared by a group of links from the transmitting node, the group of links satisfying a listed range of channel quality information, receiving downlink data on which NC is performed and decoding the downlink data based on the scheduling information.
US09509442B2
Embodiments are provided for transmitting channel information, such as control channel information, using lower resources at the transmitter combined with using apriori information associated with channel information in the decoder of the receiver. The apriori information represent predictable information that can be predicted by the receiver and is not transmitted with the channel information by the transmitter. The transmitter determines the apriori information for the channel and codes the channel information into bits and fields excluding the apriori information. Upon receiving the channel information, the receiver determines the apriori information associated in accordance with previously received information. The apriori information is then provided as probability information for input to the decoder. The decoder then decodes the received information in accordance with the apriori information.
US09509440B2
A method and radio node (500) for enabling higher-order modulation in a radio communication with a first UE (502). A first table configuration comprises at least one of a first Modulation and Coding Scheme, MCS, table and a first Channel Quality Indicator, CQI, table which tables support a certain maximum modulation order. When the radio node (500) detects that a modulation order higher than the maximum modulation order of the first table configuration is potentially possible to use in the radio communication, the radio node (500) instructs the first UE (502) to apply a second table configuration which comprises at least one of a second MCS table and a second CQI table which second tables support the higher modulation order. At least one entry for at least one modulation order in the tables of the first table configuration is maintained in the tables of the second table configuration as a fall-back in case it is desirable to use the at least one modulation order of the first table configuration when the second table configuration is applied. Thereby, a higher data rate can be achieved in the radio communication.
US09509437B2
Methods are described allowing a vector signaling code to encode multi-level data without the significant alphabet size increase known to cause symbol dynamic range compression and thus increased noise susceptibility. By intentionally restricting the number of codewords used, good pin efficiency may be maintained along with improved system signal-to-noise ratio.
US09509436B2
Techniques are disclosed for protecting communication of an NFC-enabled device by generating one or more blocking signals during an NFC data exchange. The blocking signal(s) can include a similar carrier frequency, modulation type, and/or modulation rate an NFC signal, thereby effectively masking the NFC signal. Furthermore, the blocking signal(s) can have a varying amplitude and/or length, which can further mask when an NFC signal is transmitted.
US09509434B2
Systems and methods of optimizing capacity of an optical network, through intentionally reducing margin on one or more wavelengths, include identifying a first wavelength capable of using excess capacity; determining the one or more wavelengths that have extra margin; adjusting at least one of the one or more wavelengths to reduce associated margin to a nominal margin so as to increase supportable capacity of the first wavelength; and increasing capacity of the first wavelength based on the supportable capacity.
US09509427B2
Systems and methods relating to suppressing interference during cell detection are disclosed. In some embodiments, a method of operation of a wireless device to perform cell detection comprises training one or more adaptive filters to spatially filter transmissions from one or more perceived directions of one or more sources of unknown interference and performing cell detection using the one or more adaptive filters to spatially filter transmissions from the one or more perceived directions of the one or more sources of the unknown interference. In this manner, cell detection in the presence of the unknown interference is improved.
US09509423B2
A broadcast apparatus transmits data of programs. A broadcast control apparatus measures the extent of viewing requests from users of terminals as scores for programs that are transmitted from the broadcast apparatus, and based on the scores that were measured, determines the service quality that is used in the broadcast of the programs. A communication access network apparatus, upon determination of the service quality of programs by the broadcast control apparatus, broadcasts data of programs that are received from the broadcast apparatus by communication channels having a transmission rate that corresponds to the service quality.
US09509407B2
A method and a device for conveying optical data are provided, wherein an optical network unit conveys data to a terminal via dual sideband modulation, wherein the terminal processes only the upper or only the lower sideband received from the optical network unit, and wherein several dual sideband modulated signals from several optical network units partially overlap when being received at the terminal. Furthermore, a communication system is suggested comprising at least one such device.
US09509403B2
A method and apparatus for implementing dimming are disclosed. The method includes: at an MAC layer, dividing an MSDU into two or more sub-MSDUs with a same length; encapsulating each sub-MSDU obtained after dividing into a separate MPDU, and generating a compensation frame for each MPDU; and aggregating the MPDUs and the compensation frames with the same addresses into a PSDU part of a PPDU and transmitting a physical frame.
US09509381B1
A method is provided. The method includes receiving a signal, wherein the signal includes a serving signal and an interference signal; removing the serving signal from the received signal to provide a residual signal; equalizing the residual signal based on linear estimation; determining a sample sum of the equalized signal; determining a plurality of eigenvalues from the sample sum; and estimating a transmission rank of the interference signal using hypothesis testing based on the plurality of eigenvalues.
US09509376B2
A server information handling system baseboard management controller (BMC) includes an NFC transceiver that communicates NFC signals through an NFC antenna structure. The BMC selectively configures the NFC antenna structure to isolate portions of conductive material for use as an antenna in non-NFC communications, such as wireless local area network communications (WLAN) at 2.4 or 5 GHz or wireless personal area network (WPAN) communications at 2.4 or 60 GHz. In one embodiment, WLAN and WPAN communications are encrypted with a key provided through NFC or other types of wireless communication, such as visible, infrared or ultraviolet light signals.
US09509373B2
A system can be used for contactless communication of information between a first device and a second device, each having an antenna intended to be coupled via a near magnetic field. The first device includes a transmit chain having first circuitry configured to generate a digital data stream corresponding to the information to be transmitted, and second circuitry configured to generate a first amplitude-modulated and dithered signal in the antenna of the first device from this stream and from an application of a first dithering. The second device includes a receive chain having third circuitry configured to carry out a frequency transposition of a second amplitude-modulated and dithered signal originating from the first signal, with application of a second dithering synchronous with the first dithering.
US09509369B2
This is generally directed to adjusting signaling properties based on cable attributes. In some embodiments, the cable attributes can include information such as the length of a cable, the diameter of a cable, the type of plug on a cable, the type of or presence of shielding on a cable, or any combination of the above. This information can then be used to determine the appropriate signaling properties for that cable (e.g., with respect to an EMC standard). The appropriate signaling properties may, for example, optimize the signal that is used to drive the cable while still allowing the cable to generate emissions that are within acceptable EMC standards. In some embodiments, the appropriate signaling properties can include factors such as the drive strength of the signal, the slew rate of the signal, the maximum voltage of the signal, the frequency of the signal, or any combination of the above.
US09509366B2
The present application provides an interference estimation circuit which includes a signal generator, a first symbol extractor and a first mixer. The signal generator generates an orthogonal signal orthogonal to partial symbols of a plurality of pilot signals. The first symbol extractor extracts partial symbols of a first decoded signal decoded from a received signal wherein the first decoded signal contains one of the plurality of pilot signals, and includes an input node for receiving the first decoded signal and an output node for outputting a first extracted signal. The first extracted signal is substantially orthogonal to the orthogonal signal. The first mixer is coupled to the signal generator for receiving the orthogonal signal and to the first symbol extractor for receiving the first extracted signal, and outputs a first mixed signal of the orthogonal signal and the first extracted signal for interference estimation.
US09509364B2
An integrated antenna unit, including an extra-wideband antenna, a docking station, and an integrated, field replaceable remote radio unit that electrically couples to the docking station. The docking station may be configured to receive a removable transmission circuit that that electrically couples the remote radio unit and the antenna.
US09509362B2
A transceiver processing hardware (“TPH”) configured to process wireless bit stream(s) includes a minimum mean square error (“MMSE”), an inverse discrete Fourier transform (“IDFT”), a demapper, a descrambler, and a combiner. While MMSE estimates transmit the bit stream, IDFT generates samples associated with the frequency of the bit stream. The demapper, in one embodiment, is configured to discard one or more unused constellation points relating to the frequency of bit stream from the mapping rules. The demapper, in one aspect, includes one or more minimum function components (“MFCs”) and a special treatment component (“STC”). MFCs are able to receive and compare bit stream(s) representing a symbol which corresponds to a quadrature amplitude modulation (“QAM”). STC, in one aspect, is able to force infinity values to the MFCs when the bit stream or stream of bits is identified as ACK or RI with a predefined encoding category.
US09509354B2
A homodyne receiver (100, 200, 300), comprising a first mixer (115, 215, 315) with an RF input port (105, 213, 313) and an LO input port (110, 214, 314) for an LO signal and an output port (120, 217, 317) for the output signal of the first mixer which is also arranged to be the output port of the homodyne receiver. The homodyne receiver (100, 200, 300) also comprises a control unit (125) for controlling signal leakage from the LO input port (110, 214) to the RF input port (105, 213) of the first mixer (115, 215). The control unit (125) is arranged to control the leakage in amplitude and phase so that second-order distortion products and third order distortion products which are created when the RF and LO signals are mixed in the first mixer (115, 215) exhibit similar amplitudes but a phase difference of 180 degrees.
US09509350B1
A non-linear pre-distortion engine maintaining constant peak power at its output is disclosed. The engine includes a compression estimator, a crest factor reduction processor, a digital pre-distorter and a power amplifier. The compression estimator is configured to generate a compression estimate based on an input signal and a feedback signal. The feedback signal is based on an RF output signal. The crest factor reduction processor is configured to reduce a crest factor of the input signal to generate a crest factor reduced signal based on the compression estimate. The digital pre-distorter is configured to apply a pre-distortion to the crest factor reduced signal after an initial phase and generate a pre-distorted signal based on pre-distortion parameters. The power amplifier is configured to amplify the pre-distorted signal to generate the RF output signal. The operation of the chain consisting of pre-distorter and power amplifier is substantially linear and the pre-distorter maintains constant peak power at its output, which eliminates unwanted avalanche or pre-distorter blow-up issues.
US09509338B2
A data processing device includes a compression circuit and a padding circuit. The compression circuit is configured to compare pairs of two contiguous bits within data composed of 2n bits (where n is a natural number), and compress the data based on a result of the comparison. The padding circuit is configured to generate transmission data of 2n bits by padding the compressed data with a dummy pad.
US09509337B1
A hardware data compressor that compresses an input block of characters by replacing strings of characters in the input block with back pointers to matching strings earlier in the input block. A hash table is used in searching for the matching strings in the input block. A plurality of hash index generators each employs a different hashing algorithm on an initial portion of the strings of characters to be replaced to generate a respective index. The hardware data compressor also includes an indication of a type of the input block of characters. A selector selects the index generated by of one of the plurality hash index generators to index into the hash table based on the type of the input block.
US09509330B2
Provided is an analog-to-digital converter capable of suppressing an increase in an occupation area. The analog-to-digital converter includes a multiplying digital-to-analog conversion circuit which includes a capacitance circuit that samples and amplifies an input signal, a quantizer that quantizes the input signal, and a control circuit that determines a voltage to be supplied to the capacitance circuit in accordance with an output from the quantizer. The capacitance circuit includes a first capacitance element and a second capacitance element, each of which includes a first electrode to which a normal phase signal corresponding to the input signal is supplied and a second electrode to which an opposite phase signal is supplied when the input signal is sampled. When the input signal is amplified, an output from the control circuit is supplied to the respective second electrodes, and signals from the respective first electrodes are regarded as amplified residual error amplified signal.
US09509329B2
An asynchronous successive approximation register analog-to-digital converter and an internal clock generator included in the same are disclosed. The internal clock generator in an SAR ADC comprises a detection unit configured to generate an up pulse or a down pulse by sensing generation time of a final internal clock and next external clock; and a delay block configured to increase or decrease delay time by controlling a bias voltage according to the generated up pulse or the generated down pulse.
US09509324B2
An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.
US09509321B2
A clock oscillator includes a high speed oscillator generating a high speed clock signal and comprising a digital trimming function; a counter receiving said high speed clock signal at a clock input; a time base having a low drift and controlling said counter, wherein the counter generates a difference between a reference value and a counter value; and a digital integrator receiving said difference value and providing trimming data for said high speed oscillator.
US09509317B2
A rotational synchronizer for metastability resolution is disclosed. A synchronizer includes a plurality of M+1 latches each coupled to receive data through a common data input. The synchronizer further includes a multiplexer having a N inputs each coupled to receive data from an output of a corresponding one of the M+1 latches, and an output, wherein the multiplexer is configured to select one of its inputs to be coupled to the output. A control circuit is configured to cause the multiplexer to sequentially select outputs of the M+1 latches responsive to N successive clock pulses, and further configured to cause the M+1 latches to sequentially latch data received through the common data input.
US09509305B2
In an embodiment, an electronic device includes an integrated circuit (IC) having a plurality of power domains, a first regulator coupled to a given power domain, a second regulator coupled to the given power domain, and a switching circuit coupled between the first and second regulators and configured to control an amount of current drawn by the power domain from the first and/or second regulators. In another embodiment, a method includes controlling an impedance of a switching circuit to change an amount of current, the switching circuit coupled to a given power domain of an IC configured to operate in a first mode followed by a second mode, where the switching circuit is coupled to a first regulator configured to provide more power to the IC than a second regulator, and a transition period includes turning off the first regulator and turning on the second regulator.
US09509304B2
An induction generator, for a wireless switch, having a magnetic element with north pole and south pole contact sections, and a coil core having pole contact sections, which can contact with the north pole contact section and the south pole contact section. The magnetic element and the coil core are disposed so as to be movable relative to one another so that a reversal of the magnetic flux direction in the coil core can be generated when switching between first and second idle position, which define a direction of relative movement, in which the north pole and the south pole contact sections each contacts the respective associated pole contact sections. The induction generator has a magnetizable sliding contact section for sliding guidance of the relative movement between the coil core and magnetic element, and this sliding contact section extends parallel to the direction of movement.
US09509296B1
Systems and methods herein may include or involve control circuitry that detects missing edges of reference and/or feedback clocks and may block the next N rising edges of the feedback clock or reference clock, respectively. In some implementations, a phase frequency detector (PFD) circuit comprises first circuitry including an output that outputs a missing edge signal. The first circuitry may include components arranged to detect a missing rising edge of one or both of a reference clock signal and a feedback clock signal. Second circuitry is coupled to the first circuitry and may include components arranged to generate one or both of a reference clock blocking signal and a feedback clock blocking signal based on the missing edge signal. Further, in some implementations, the blocking of the next N rising edges of the opposite clock may effectively increase the positive gain of the PFD.
US09509293B2
Embodiments of the present invention disclose a method and an apparatus for controlling chip performance, and relate to the field of communications technologies, which solves a problem in the prior art that a chip is reset or performance is greatly decreased as long as a temperature of the chip is higher than a preset threshold. The method includes: obtaining a working temperature of a chip; when the working temperature of the chip reaches one of multiple preset temperature thresholds, obtaining, according to preset correspondence between a temperature threshold and a chip performance control policy, a chip performance control policy that corresponds to the one of the multiple temperature thresholds; and controlling working of the chip according to the control policy. The present invention is applicable to an electronic device to which a chip is applied, such as a desktop computer or a notebook computer.
US09509280B1
A technique relates to a microwave device. A qubit is connected to a first end of a first coupling capacitor and a first end of a second coupling capacitor. A resonator is connected to a second end of the first coupling capacitor and a second end of the second coupling capacitor. The resonator includes a fundamental resonance mode. A filter is connected to both the qubit and the first end of the first or second coupling capacitor.
US09509273B2
A transformer filter arrangement including a transformer having a first winding and a second winding is provided. Both of the first and the second windings are located between an outer border and an inner border, which is inside the outer border. The transformer filter arrangement further includes at least one reactive sub circuit, each including at least one inductor. The first winding of the transformer is divided into a plurality of winding segments. At least a first one of the at least one reactive sub circuit being connected in series with the winding segments of the first winding between two such winding segments, and having at least one of the at least one inductor located inside said inner border.
US09509243B2
A self-calibrating linear actuator is configured to control a spring return valve with variable stroke. The actuator includes a motor, a spindle coupled to an output of the motor, a motor controller coupled to the motor, a microcontroller coupled to the motor controller, and a back electromotive force (BEMF) circuit, coupled to the motor, configured to provide to the microcontroller a BEMF value for each motor step. The microcontroller is configured to determine a difference of a number of motor steps during operation of the actuator and to store the difference as a calibrated touch point for the actuator.
US09509242B2
A method for operating a direct current (DC) motor is shown and described. The method includes generating a first pulse width modulated (PWM) signal having a first duty cycle, providing the first PWM signal as a PWM DC output for the DC motor, and adjusting the first duty cycle to control a speed of the DC motor. The method further includes sensing an electric current output to the motor using a current sensor and, when the sensed current exceeds a threshold, holding the PWM DC output off.
US09509241B2
A control method used in a control unit of a power converter, connected by three output phases to a synchronous electric motor, the method being used for starting the motor and including a first step for determining the voltages to be applied to the output phases depending on a reference current, a second step for determining a frequency to be applied to the stator depending on a stator frequency, a step for application of the first step and the second step for a given duration, so as to allow the rotor of the synchronous electric motor to rotate at the stator frequency applied. The method is particularly effective for an architecture including a transformer and a sinus filter between the power converter and the electric motor.
US09509208B2
A load driving device according to the present invention has: an internal circuit (DRV) that operates in response to the supply of a power supply voltage (HV or LV); an output circuit (PD1 and PD2) for driving a load in response to the supply of the power supply voltage (HV or LV); an abnormality detection circuit (12) for monitoring the power supply voltage (HV or LV) and generating an abnormality detection signal (S1); and a power supply switch (P0) for, according to the abnormality detection signal (S1), conducting or cutting off a power-supply-voltage supply line to the internal circuit (DRV).
US09509206B2
A power factor corrector correcting the power factor of an alternating current (AC) voltage is disclosed. A power factor correcting unit corrects the power factor of the AC voltage. A smoothing unit smoothes a power factor corrected voltage and includes a film condenser and a plurality of electrolytic condensers. A rectified voltage is applied to one end of an inductor. One end of a switch is connected to the other end of the inductor, and the other end of the switch is earthed. One end of a diode is connected to one end of the switch. One end of a film condenser is connected to the other end of the diode, and the other end of the film condenser is earthed. An electrolytic condenser is parallel-connected to the film condenser.
US09509197B2
The manufacturing apparatus for a stator core has a servo pressing device, a mold, a punch assembly, a first cylinder, a second cylinder and a third cylinder. The mold is mounted on the servo pressing device and has an upper seat and a lower seat. The punch assembly is mounted in the upper seat. The first cylinder, the second cylinder and the third cylinder are mounted on the mold. The stator laminations are respectively punched by the punch assembly of the manufacturing apparatus, and are automatically stacked in the mold. The groups of stator laminations stacked in the recess are respectively pushed by the second cylinder and respectively pressed by the third cylinder. The stator laminations are automatically stacked and pressed in the mold without manpower. Therefore, the manufacturing apparatus of stator core can save manpower and reduce the equipment cost.
US09509187B2
Exemplary embodiments relate to a hollow-cylindrical coreless winding for an electric motor. The winding includes a plurality of single coils which are distributed across the circumference of the winding, wherein each single coil includes a plurality of turns which are spirally wound around a winding axis which is perpendicular to an axis of the winding. Successive single coils overlap in a roof tile manner. The winding includes at least two phase windings, each of the phase windings consisting of several ones of the single coils. The phase windings are offset with respect to each other in the circumferential direction of the hollow-cylindrical winding, so that the single coils of a first phase winding are disposed in the circumferential direction of the hollow-cylindrical winding between the single coils of a second phase winding. Each of the phase windings is wound from a continuous wire.
US09509186B2
A reduced weight rotor design for use in an electric motor where the reduced weight rotor maintains its structural integrity. The reduced weight rotor includes a center hub, an outer ring having lobed portions extending inwardly towards the hub and located adjacent to each location of a magnetic pole pairing, and spokes connecting the hub to the outer ring where the spokes are arranged in a number of pairs equal to the total number of the magnetic pole pairings and wherein each spoke of a given pair does not cross each other spoke of the given pair but does cross a spoke of an adjacent pair thereby forming a one cross spoke pattern.
US09509178B2
A system attached to an object for communicating the object information to communication devices. The system includes an electronic circuitry to communicate an identification-information, and a hub section coupled to the communication device to power the electronic circuitry and further receives the identification-information transmitted from the electronic circuitry. The electronic circuitry may be embedded in a single chip/printed decal/flexible polymer foil. The hub section includes a generator, a first converter, a first switching unit, a first electrode, a first detection unit, and a hub controller. The electronic circuitry includes a second electrode, a floating electrode, a second converter, a buffer, a second detection unit, a modulation unit, and an analog processing unit. The hub controller authenticates the electronic circuitry on receiving the modulated identification-information; further the hub controller communicates the object information to the electronic circuitry and the communication devices based on the modulated identification-information.
US09509175B2
The present invention relates to a gas turbine power generation system, that includes a hydrogen-cooled generator having hydrogen as coolant, a plant hydrogen storage, generator auxiliaries and an emergency power supply system. The power generation system includes a fuel cell using hydrogen as fuel. The fuel cell is supplied via a line with hydrogen fuel from the hydrogen filling of the hydrogen-cooled generator in case of failure or disruption of the power supply from the gas turbine power generation system. In a preferred embodiment the fuel cell is supplied with additional hydrogen via a line from the plant hydrogen storage and/or with additional hydrogen via a line from generator auxiliaries in case of failure or disruption of the power supply from the gas turbine power generation system.
US09509168B2
The embodiments described herein provide a power transmitter for wireless charging of an electronic device and methods of its operation. The power transmitter uses an inverter configured to generate a square wave from a potentially wide ranging DC input voltage. The inverter is configured to generate the square wave with a duty cycle that results in a desired equivalent voltage output, effectively independent of the DC input voltage that is provided. Thus, by generating a square wave with a selectable duty cycle the inverter provides the ability to facilitate wireless power transfer with a wide range of DC input voltages. Furthermore, in some embodiments the power transmitter may provide improved power transfer efficiency using a quasi-resonant phase shift control strategy with adjustable dead time and a matching network that is dynamically selectable to more effectively couple with the transmitter coil combination being used to transmit power to the electronic device.
US09509147B2
Disclosed is an apparatus for use in wireless energy transfer, which includes a first resonator structure configured to transfer energy non-radiatively with a second resonator structure over a distance greater than a characteristic size of the second resonator structure. The non-radiative energy transfer is mediated by a coupling of a resonant field evanescent tail of the first resonator structure and a resonant field evanescent tail of the second resonator structure.
US09509142B2
A method and apparatus for correcting a locally measured inverter voltage. In one embodiment, the method comprises determining a voltage compensation to compensate for a voltage drop along an AC bus between an inverter and a remotely located point on the AC bus; obtaining a voltage measurement at the inverter; applying the voltage compensation to the voltage measurement to determine a corrected voltage measurement; comparing the corrected voltage measurement to a voltage requirement; and performing a corrective action at the inverter when the corrected voltage measurement does not meet the voltage requirement.
US09509123B2
Methods and systems include generating one or more mid-infrared frequencies based at least upon electron transitions in one or more quantum cascade heterostructures. The quantum cascade heterostructures are concurrently configured with a significant second-order nonlinear susceptibility, a significant third-order nonlinear susceptibility, and an insignificant group velocity dispersion. A set of mid-infrared frequencies (that may include a frequency comb) is generated in the quantum cascade heterostructures based at least upon a four-wave mixing of the one or more mid-infrared frequencies. The four-wave mixing arises at least from the significant third-order nonlinear susceptibility and the insignificant group velocity dispersion. A set of terahertz frequencies (that may include a frequency comb) is generated in the quantum cascade heterostructures based at least upon a difference frequency generation from mid-infrared frequency pairs selected from the set of mid-infrared frequencies. The difference frequency generation arises at least from the significant second-order nonlinear susceptibility.
US09509121B2
A semiconductor laser element includes: a semiconductor-layered structure including a waveguide core layer and having a distributed feedback laser portion and a distributed Bragg reflection portion, the waveguide core layer having a length continuous in an optical cavity length direction and a diffraction grating layer being disposed in vicinity of the waveguide core layer and along the waveguide core layer in the distributed feedback laser portion, and the waveguide core layer being disposed discretely and periodically to form a diffraction grating in the distributed Bragg reflection portion; and an electrode for injecting a current to the distributed feedback laser portion. The distributed feedback laser portion oscillates a laser light at a wavelength corresponding to a period of the diffraction grating layer. The diffraction grating formed by the waveguide core layer in the distributed Bragg reflection portion is set to have a stop band including the wavelength of the laser light.
US09509113B2
Methods and systems for transient gain cancellation at an optical amplifier may involve generating saturating light that is introduced in a reverse direction to a transmission direction at a doped fiber amplification element. The doped fiber amplification element may amplify an input optical signal having a plurality of wavelengths as well as the saturating light. The saturating light may be regulated by a control circuit to counteract transient gain effects of add/drop events in the input optical signal. The saturated light may be filtered to achieve a desired spectral profile.
US09509108B2
The invention relates to a bus connector system having a bus circuit board for producing an electrical connection between electrical equipment, the bus circuit board being attached in a removable manner to a housing of the electrical equipment.The underlying idea of the present invention is advantageously based on the bus circuit board being connected directly to the housing of the electrical equipment. Thus, no support rail is necessary for producing the electrical contact between the equipment.
US09509105B2
A receptacle, fixed to a first case, has a central conductor portion, an outer conductor portion that concentrically surrounds the central conductor portion, and a receptacle-side convex portion that extends in a connector circumferential direction and is formed on a top end portion of the outer conductor portion. A plug, fixed to a second case, has a plurality of inner contact pieces that make contact with an outer peripheral surface of the central conductor portion with fitting into the receptacle, a plurality of outer contact pieces that extend in a connector axial direction on an outer peripheral surface of the outer conductor portion with intervals therebetween, and plug-side convex portions that are freely displaceable in the connector axial direction in a state of being in surface contact with the outer peripheral surface of the outer conductor portion and are formed on the outer contact pieces of the plug.
US09509101B2
A modular electrical connector with separately shielded signal conductor pairs. The connector may be assembled from modules, each containing a pair of signal conductors with surrounding partially or fully conductive material. Modules of different sizes may be assembled into wafers, which are then assembled into a connector. Wafers may include lossy material. In some embodiments, shielding members of two mating connectors may each have compliant members along their distal portions, such that, the shielding members engage at points of contact at multiple locations, some of which are adjacent the mating edge of each of the mating shielding members.
US09509100B2
An electrical connector includes a housing, signal modules, and ground plates. The signal modules and ground plates are arranged in a pattern that includes ground plates flanking corresponding pairs of signal modules within the housing. The signal modules have a dielectric body and signal conductors held within the dielectric body. The signal conductors include contact beams protruding from a front edge for electrical termination. Each ground plate has contact beams aligned with the contact beams of the signal modules to provide shielding therebetween. Each signal module has a lateral thickness that is greater than a thickness of each ground plate. The signal conductors of each signal module are offset relative to a central plane of the signal module such that contact spacings between adjacent contact beams are uniform. Optionally, ground tie bars extend through the signal modules and ground plates to electrically common the ground plates.
US09509096B2
A manual service disconnect for a battery system includes a disconnect header having a housing defining a receptacle, a high current terminal connector within the receptacle, a high voltage interlock (HVIL) connector within the receptacle and a control device terminal connector within the receptacle. A disconnect plug is removably coupled to the disconnect header. The disconnect plug has a high current fuse electrically connected to the high current terminal connector and a HVIL shunt terminal electrically connected to the HVIL connector. A current power control device is received in the receptacle and is electrically connected to the control device terminal connector. The current power control device is exposed for servicing when the disconnect plug is removed from the disconnect header and the current power control device is inaccessible when the disconnect plug is coupled to the disconnect header.
US09509091B2
A connector assembly includes a first connector having a first terminal and a second terminal which are used for fitting detection, a second connector fitted with the first connector, a manipulation lever for use in fitting the second connector with the first connector along a fitting direction, a fitting lock mechanism adapted to lock a fitting state of the first connector and the second connector and a fitting detection mechanism disposed at the second connector and adapted to short-circuit between the first terminal and the second terminal when the first connector and the second connector are fitted with each other, the fitting detection mechanism having a first contact point, a second contact point and a third contact point that are arranged in series between the first terminal and the second terminal when the first connector and the second connector are fitted with each other.
US09509078B2
A connector housing is provided capable of reliably preventing a terminal fitting from being inserted and accommodated in a vertically inverted posture into a cavity. A connector housing includes a cavity capable of accommodating a terminal fitting provided with a projection on an outer side surface of a terminal main body portion in the form of a rectangular tube. The cavity includes a main body accommodating portion into which the terminal main body portion is to be accommodated and a groove portion into which the projection is insertable and movable forward when the terminal fitting is inserted in a proper posture into the cavity. A guiding portion for angularly displacing the terminal main body portion by coming into contact with the projection when the terminal fitting is inserted in a vertically inverted posture into the cavity is provided on a side of the cavity before the main body accommodating portion.
US09509069B2
An electrical connector is disclosed having a housing and a female terminal. The housing has an assembly receiving space. The female terminal is positioned in the assembly receiving space and has a first female terminal, a second female terminal, and an elastic connecting spring. The first female terminal has a first contact receiving space. The second female terminal has a second contact receiving space and is independently displaceable relative to the first female terminal along a longitudinal axis. The elastic connecting spring connects the first female terminal to the second female terminal.
US09509066B2
A connector that can adjust a force for inserting a terminal includes a base and a spring. The spring has a bend portion bent from the edge of the base and an abutment portion continued from the bend portion. The spring extends along the base and is sandwiched between the base and the abutment portion. A terminal is inserted toward the bend portion from an opening located on an opposite side of the bend portion and formed between the base and the abutment portion.
US09509063B2
A wireless communication arrangement (100a) with multiple antennas for a vehicle includes a first printed circuit board (110) having a modem unit (111) and a radiating antenna element (113); a second printed circuit board (120) having a radiating antenna element (123); an interface unit (112) disposed on the first printed circuit board (110) and/or the second printed circuit board (120); and a main bendable portion (130) bendably and electrically connecting the first printed circuit board (110) and the second primed circuit board (120) to each other. The first printed circuit board (110) and the second printed circuit board (120) are mountable on an outer surface of a vehicle in non-horizontal orientation with respect to said outer surface, with the first printed circuit board (110) and the second printed circuit board (120) forming a convex like shape in a horizontal direction via bending of the main bendable portion (130).
US09509048B2
According to one embodiment, an antenna includes a second element that has an end connected to a first point of a first element, and first and second ends kept open, and includes a first portion extending from a feed terminal to the first end, and a second portion extending from the feed terminal and bifurcated at a second point between the first point and the first end. The lengths of the first and second portions are set to substantially ¼ of a resonance frequency, and substantially ¾ of a resonance frequency, severally. The second portion includes a portion extending from the feed terminal to the second point, and a portion extending from the second point to the second end and interposed between the portion and a ground.
US09509038B2
Vehicle window glass include a glass plate, a dielectric, a conductive film, placed between the glass plate and the dielectric, and an antenna including a pair of electrodes. The conductive film, includes a pair of facing parts that faces the electrodes across the dielectric, a main slot, and a pair of sub slots. The main slot has, at one end, an open end open at an outer edge of the conductive film, and is formed between the facing parts. Each sub slot has, at one end, an open end open at the outer edge of the conductive film. One of the sub slots connects, at the other end, to the main slot so as to surround one of the facing parts. The other of the sub slots connects, at the other end, to the main slot so as to surround the other of the facing parts.
US09509036B2
A communications unit. At least one example includes a platform that has a tower assembly operably coupled thereto such that tower assembly is movable between a horizontally deployed position and a vertically deployed position relative to the platform. The tower assembly includes a plurality of telescoping tower segments that are movably supported relative to each other such that they may be selectively manually deployed between a retracted position and the horizontally deployed position. The unit may further include a locking assembly that is configured to selectively and individually lock each of the plurality of telescoping tower segments in the horizontally deployed position. A deployment assembly operably interfaces with the tower assembly and is configured to selectively move the tower assembly between the horizontally deployed position and the vertically deployed position.
US09509030B2
Various embodiments of the invention include a power management unit (PMU) to simultaneously control the production of hydrogen and electricity for external use in an MFC-MEC coupled system. In one embodiment, the PMU includes low voltage electronic switches using MOSFETs, and a PWM controller. The PWM controller creates timing waveform necessary to operate the switches. In other embodiments, the switches can be replaced by any switching regulator capable of operating at low operating voltage and currents that yield high efficiency. Such a system can be used in a waste-water treatment facility.
US09509028B2
A microbial battery is provided. At the anode, microbial activity provides electrons to an external circuit. The cathode is a solid state composition capable of receiving the electrons from the external circuit and changing from an oxidized cathode composition to a reduced cathode composition. Thus, no external source of oxygen is needed at the cathode, unlike conventional microbial fuel cells. The cathode can be removed from the microbial battery, re-oxidized in a separate oxidation process, and then replaced in the microbial battery. This regeneration of the cathode amounts to recharging the microbial battery.
US09509027B2
A metal-air battery including: a negative electrode metal layer; a negative electrode electrolyte layer disposed on the negative electrode metal layer; a positive electrode layer disposed on the negative electrode electrolyte layer, the positive electrode layer comprising a positive electrode material which is capable of using oxygen as an active material; and a gas diffusion layer disposed on the positive electrode layer, wherein the negative electrode electrolyte layer is between the negative electrode metal layer and the positive electrode layer; wherein the negative electrode metal layer, the negative electrode electrolyte layer, and the positive electrode layer are disposed on the gas diffusion layer so that the positive electrode layer contacts a lower surface and an opposite upper surface of the gas diffusion layer, and wherein one side surface of the gas diffusion layer is exposed to an outside.
US09509024B2
A secondary battery including a positive and negative electrode, a separator, an electrolyte, and a gas mitigation device is disclosed. The gas mitigation device may include a catalyst configured to catalyze a reaction to form a solid phase material from one or more gases generated during operation of the battery. The battery may also include a protective enclosure surrounding the catalyst, the protective enclosure being gas permeable and liquid impermeable and preventing contact between the catalyst and the electrolyte. The battery may further include a seed material configured to react with the one or more gases to form the solid phase material, which may also be included within the protective enclosure. The catalyst may include nickel nanoparticles or carbonic anhydrase and the seed material may include iron, magnesium, or calcium. In one embodiment, the solid phase material formed is a metal carbonate.
US09509013B2
According to one embodiment, there is provided a non-aqueous electrolyte secondary battery including a positive electrode including a positive electrode active material layer, a negative electrode including a negative electrode active material layer, and a non-aqueous electrolyte. At least one of the positive electrode active material layer and the negative electrode active material layer contains carbon dioxide and releases the carbon dioxide in the range of 0.1 ml to 10 ml per 1 g when heated at 350° C. for 1 minute.
US09509009B2
The present disclosure provides a method of generating electricity from a long chain hydrocarbon, said method comprising contacting the liquid non-polar substrate with a plurality of enzymes, wherein at least one enzyme is non-electric current/potential enzyme that functions as a catalyst for chemical reaction transforming a first substrate or byproduct to a second substance that can be used with an additional electric current/potential generating enzyme.
US09509008B2
A polybenzimidazole based polymer in which substituted or non-substituted benzyl groups are introduced to the two nitrogen atoms of benzimidazole ring. The benzimidazole ring is not decomposed by the attack of hydroxide ions but shows excellent alkali resistance, and thus maintains high ion conductivity. The polybenzimidazole based polymers are particularly useful for not only solid alkali exchange membrane fuel cells (SAEMFC) but also various industrial fields in which polybenzimidazole based polymers are used.
US09509005B2
A fuel cell system suppresses the deterioration of an electrolyte membrane of a fuel cell. The fuel cell system comprises: a temperature rise speed calculation unit for calculating a target temperature rise speed of the fuel cell using a temperature of the fuel cell and a water content of the fuel cell; and a drive control unit for controlling a drive of the cooling water pump using the temperature rise speed of the fuel cell and the target temperature rise speed calculated by the temperature rise speed calculation unit. The drive control unit controls the drive of the cooling water pump such that a circulation amount of the cooling water is decreased when the temperature rise speed of the fuel cell is below the target temperature rise speed and controls the drive of the cooling water pump such that the circulation amount of the cooling water is increased when the temperature rise speed of the fuel cell is equal to or greater than the target temperature rise speed.
US09508999B2
An exemplary device for managing moisture content within a fuel cell includes a reactant distribution plate having a plurality of members that establish reactant flow channels that are open on at least one side of the plate. A wicking layer is against the one side of the plate. The wicking layer includes a first portion that is uninterrupted and covers over at least some of the channels. A second portion of the wicking layer extends along ends of at least some of the members such that sections of the channels coextensive with the second portion are open toward the one side.
US09508993B2
Disclosed is an electrode for secondary batteries including an electrode mixture including an electrode active material, binder and conductive material coated on a current collector. The present invention provides an electrode for secondary batteries wherein an electrode active material is a cathode active material and/or anode active material, and the conductive material is included in an amount of 0.1 to 15% based on total weight of the electrode mixture, and a secondary battery including the same.
US09508981B2
According to one embodiment, a non-aqueous electrolyte battery is provided. The non-aqueous electrolyte battery includes a negative electrode contained a negative electrode active material. The negative electrode active material includes a monoclinic β-type titanium-based oxide or lithium titanium-based oxide. The monoclinic β-type titanium-based oxide or lithium titanium-based oxide has a peak belonging to (011), which appears at 2θ1 in a range of 24.40° or more and 24.88° or less, in an X-ray diffraction pattern obtained by wide angle X-ray diffractometry using CuKα radiation as an X-ray source.
US09508976B2
Implementations of the present disclosure generally relate to separators, high performance electrochemical devices, such as, batteries and capacitors, including the aforementioned separators, and methods for fabricating the same. In one implementation, a separator for a battery is provided. The separator comprises a substrate capable of conducting ions and at least one dielectric layer capable of conducting ions. The at least one dielectric layer at least partially covers the substrate and has a thickness of 1 nanometer to 2,000 nanometers.
US09508975B1
A nonaqueous electrolyte secondary battery separator is a porous film containing a polyolefin as a main component. The nonaqueous electrolyte secondary battery separator (i) has a phase difference of 80 nm or less with respect to light having a wavelength of 590 nm in a state where the nonaqueous electrolyte secondary battery separator is impregnated with ethanol and (ii) has a porosity of 30% to 60%.
US09508960B2
The present application provides a method for packaging a display device and an apparatus therefor. The method includes: providing a display device, a platform, a laser beam and a magnetic mechanism; wherein the display device includes a light emitting element, the light emitting element includes at least one effective light emitting region thereon and is prepared on an upper surface of a glass substrate, the glass substrate is bonded to a glass cover plate via a sealing adhesive layer; the display device is placed on the platform; the laser beam penetrates the glass cover plate and focuses on the sealing adhesive layer to sinter the sealing adhesive layer; and the magnetic mechanism clamps the glass cover plate and the glass substrate from top to bottom and applies a uniform pressing force on the effective light emitting region of the display device.
US09508956B2
An organic light emitting diode, which is a top emission-type, is configured so that at least the following are laminated on the substrate: a reflective layer including a metal material; an anode conductive layer including a transparent conductive material; an organic EL layer having a light emitting layer which contains an organic light emitting material; and a cathode conductive layer in which a semi-transmissive metal layer and a transparent conductive layer including a transparent conductive material are laminated. On the surface of the semi-transmissive metal layer that is in contact with the transparent conducive layer side, a two-dimensional lattice structure is formed in which a plurality of protrusions are arranged periodically and two-dimensionally.
US09508952B2
An organic light emitting display device includes a first substrate, a second substrate, and an array of organic light emitting elements formed over the first substrate and interposed between the first and second substrate. The array comprises a pixel defining layer. The organic light emitting display device further includes a recess formed into the pixel defining layer, a sealing member, and a reinforcing member. The sealing member is formed along the edges of the first and second substrates and interconnects the first and second substrates. The reinforcing member comprises a first portion positioned in the recess and a second portion projected outside the recess toward the second substrate such that the second portion of the reinforcing member is capable of supporting the second substrate when the second substrate is pressed toward the first substrate by an external force.
US09508949B2
An organic light emitting device includes a first electrode, a second electrode, and two or more organic material layers provided between the first electrode and the second electrode. The organic material layer includes a light emitting layer, and a mixed layer including one or more hole transfer materials and one or more electron transfer materials.
US09508945B2
A photodetector device includes multiple organic photodetector subcells arranged in a stack, each organic photodetector subcell being configured to generate an electrical current in response to absorbing light over a corresponding range of wavelengths, in which each organic photodetector subcell includes at least one electron donor material and at least one electron acceptor material.
US09508942B2
A charge transporting, liquid crystal photoalignment material comprising a charge transporting moiety connected through covalent chemical bonds to a surface derivatizing moiety, and a photoalignment moiety connected through covalent chemical bonds to a surface derivatizing moiety.
US09508929B2
A method for making phase change memory cell includes following steps. A carbon nanotube wire is located on a surface of the substrate, wherein the carbon nanotube wire includes a first end and a second end opposite to the first end. A bending portion is formed by bending the carbon nanotube wire. A first electrode, a second electrode, and a third electrode are applied on the surface of the substrate, wherein the first electrode is electrically connected to the first end, the second electrode is electrically connected to the second end, and the third end is spaced from the bending portion of the carbon nanotube wire. A phase change layer is deposited to cover the bending structure and electrically connects to the third electrode.
US09508925B2
Provided is a magnetic memory device. The magnetic memory device includes a first magnetization layer, a tunnel barrier disposed on the first magnetization layer, a second magnetization layer disposed on the tunnel barrier, and a spin current assisting layer disposed on at least a portion of a sidewall of the second magnetization layer.
US09508922B2
According to one embodiment, a magnetic memory device includes a first stack structure including a first magnetic layer, and a first nonmagnetic layer provided on the first magnetic layer, a second stack structure including a second magnetic layer provided on the first nonmagnetic layer, a second nonmagnetic layer provided on the second magnetic layer, and a top conductive layer provided on the second nonmagnetic layer, and a sidewall conductive layer provided on a sidewall of the second stack structure.
US09508912B2
A thermoelectric conversion device includes a perovskite film over a substrate and formed with first and second electrodes on the perovskite film, wherein the perovskite film includes a domain having a crystal orientation different from a crystal orientation of a crystal that constitutes the perovskite film.
US09508904B2
Methods are disclosed including generating a substrate surface topography that includes a mounting portion that is higher than a relief portion that defines a perimeter of the mounting portion.
US09508893B2
There is provided a method for manufacturing a nanostructure semiconductor light emitting device, including: forming a mask having a plurality of openings on a base layer; growing a first conductivity-type semiconductor layer on exposed regions of the base layer such that the plurality of openings are filled, to form a plurality of nanocores; partially removing the mask such that side surfaces of the plurality of nanocores are exposed; heat-treating the plurality of nanocores after partially removing the mask; sequentially growing an active layer and a second conductivity-type semiconductor layer on surfaces of the plurality of nanocores to form a plurality of light emitting nanostructures, after the heat treatment; and planarizing upper parts of the plurality of light emitting nanostructures such that upper surfaces of the nanocores are exposed.
US09508892B2
Nano-crystalline core and nano-crystalline shell pairings having group I-III-VI material nano-crystalline cores, and methods of fabricating nano-crystalline core and nano-crystalline shell pairings having group I-III-VI material nano-crystalline cores, are described. In an example, a semiconductor structure includes a nano-crystalline core composed of a group I-III-VI semiconductor material. A nano-crystalline shell composed of a second, different, group I-III-VI semiconductor material at least partially surrounds the nano-crystalline core.
US09508888B2
A solar cell is provided with: a semiconductor substrate; an insulating layer formed of a silicon compound or a metal compound, and having a predetermined pattern over the substrate; and a surface covering layer formed of an amorphous semiconductor, having a same pattern as the insulating layer, and that directly contacts the insulating layer.
US09508886B2
A method for making a crystalline silicon solar cell substrate is provided. A doped dielectric layer is deposited over the backside surface of a crystalline silicon substrate, the doped dielectric layer having a polarity opposite the polarity of the crystalline silicon substrate. Portions of the backside surface of the crystalline substrate are exposed through the doped dielectric layer. An overlayer is deposited over the doped dielectric layer and the exposed portions of the backside surface of the crystalline silicon substrate. Pulsed laser ablation of the overlayer is performed with a flat top laser beam on the silicon substrate to form continuous base openings nested within the exposed portions of the backside surface of the crystalline silicon substrate, the flat top laser beam having a beam intensity profile flatter as compared to a Gaussian beam intensity profile and having a rectangular beam cross section. Doped base regions are formed in the crystalline silicon substrate through the continuous base openings.
US09508882B2
A solar cell module includes a solar cell panel including a plurality of solar cells and a bus bar connected to the solar cells, a protective substrate on the solar cell panel, and a spacer part between the solar cell panel and the protective substrate. The spacer part includes an air layer and a spacer surrounding the air layer.
US09508865B2
According to example embodiments, a transistor includes a gate, a channel layer that is separate from the gate, a gate insulating layer between the gate and the channel layer, and a source electrode and a drain electrode respectively contacting a first region and a second region of the channel layer. The gate insulating layer includes an impurity metal containing region that includes an impurity metal and contacts the channel layer. The gate insulating layer includes an impurity metal non-containing region contacting the gate that is not doped with the impurity metal.
US09508857B2
A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.
US09508855B2
A liquid crystal display includes: a substrate; a thin film transistor disposed on the substrate; a pixel electrode connected to the thin film transistor; and a roof layer facing the pixel electrode. A plurality of microcavities are between the pixel electrode and the roof layer. A liquid crystal material is in the microcavities, and a dent is formed in the roof layer.
US09508848B1
One illustrative method disclosed herein includes, among other things, removing at least a portion of a vertical height of portions of an overall fin structure that are not covered by a gate structure so as to result in the definition of a remaining portion of the overall fin structure that is positioned under the gate structure, wherein the remaining portion comprises a channel portion and a lower portion located under the channel portion. The method continues with the formation of a layer of heat-expandable material (HEM), performing a heating process on the HEM so as to cause the HEM to expand, recessing the HEM so as to expose edges of the channel portion and growing a semiconductor material above the HEM using the exposed edges of the channel portion as a growth surface.
US09508844B2
A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
US09508843B2
A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer.
US09508840B2
High frequency currents may be rectified by means of a printable diode comprising a first and a second electrode, between which a semiconducting layer comprising semiconducting particles embedded in an inert matrix, and a conducting layer comprising conducting particles embedded in an inert matrix are arranged.
US09508838B2
A vertical III-nitride field effect transistor includes a drain comprising a first III-nitride material, a drain contact electrically coupled to the drain, and a drift region comprising a second III-nitride material coupled to the drain and disposed adjacent to the drain along a vertical direction. The field effect transistor also includes a channel region comprising a third III-nitride material coupled to the drift region, a gate region at least partially surrounding the channel region, and a gate contact electrically coupled to the gate region. The field effect transistor further includes a source coupled to the channel region. The source includes a GaN-layer coupled to an InGaN layer. The channel region is disposed between the drain and the source along the vertical direction such that current flow during operation of the vertical III-nitride field effect transistor is along the vertical direction.
US09508837B2
To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.
US09508835B2
A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.
US09508834B1
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, wherein the fin-shaped structure comprises a top portion and a bottom portion; removing part of the STI to expose the top portion of the fin-shaped structure; and performing an oxidation process on the exposed top portion of the fin-shaped structure to divide the top portion into a first top portion and a second top portion while forming an oxide layer around the first top portion.
US09508832B2
A method of fabricating a semiconductor device includes forming a channel layer on a substrate, forming a sacrificial layer on the channel layer, forming a hardmask pattern on the sacrificial layer, and performing a patterning process using the hardmask pattern as an etch mask to form a channel portion with an exposed top surface. The channel and sacrificial layers may be formed of silicon germanium, and the sacrificial layer may have a germanium content higher than that of the channel layer.
US09508827B2
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; forming a lightly doped drain in the substrate; and performing a first implantation process for implanting fluorine ions at a tiled angle into the substrate and part of the gate structure.
US09508798B2
According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of a second conductivity type, an insulating section, and a semiconductor section. The second semiconductor region is provided on the first semiconductor region. A carrier concentration of the first conductivity type of the second semiconductor region is lower than a carrier concentration of the first conductivity type of the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating section is provided around the first semiconductor region and the second semiconductor region. The insulating section is in contact with the second semiconductor region. The semiconductor section is provided around the insulating section. The semiconductor section is not in contact with the first semiconductor region.
US09508784B2
An organic EL display device includes an inorganic insulating film including a contact part as an opening where a contact electrode made of a conductive film is exposed, a TFT circuit layer provided on the inorganic insulating film and including a circuit including a thin film transistor, an organic EL element layer provided on the TFT circuit layer and including an organic EL element whose light emission is controlled by the circuit, and a sealing layer covering the organic EL element layer and made of an inorganic insulating material.
US09508783B2
A display panel and fabrication method is provided. The display panel may include a substrate, and the substrate includes a display region and a border region surrounding the display region. The display panel also include a heat transfer pattern formed in the border region of the substrate to transfer and dissipate heat generated during a laser cutting process when forming the display panel. The heat transfer pattern includes at least one metal layer.
US09508779B2
Embodiments of the disclosure disclose an electroluminescence display device and a fabrication method thereof. The electroluminescence display device comprises an opposed substrate (20) and an array substrate (10). The array substrate (10) comprises: a first substrate (11), and a thin film transistor (12), a first protective layer (131) and a first connection electrode (141) sequentially disposed on the first substrate (11). The first connection electrode (141) is connected to a drain electrode of the thin film transistor (12). The opposed substrate (20) comprises: a second substrate (21), and a first electrode (24), an organic electroluminescence layer (25) and a second electrode (26) sequentially disposed on the second substrate (21). The second electrode (26) and the first connection electrode (141) are connected with each other by a conductive adhesive (40). Thereby, the reliability of the electrical connection between the thin film transistor and the second electrode is enhanced, a film-forming time in the fabrication process of the connection electrode is shortened, and etching difficulty of the connection electrode reduced, and thus the productivity is improved.
US09508778B2
An organic light emitting device includes: a first substrate; a plurality of electrodes on the first substrate; a pixel definition layer on the plurality of electrodes and including a plurality of openings and respectively exposing the plurality of electrodes; and a spacer on the pixel definition layer, wherein the pixel definition layer includes a first opening and a second opening adjacent to each other along a first direction by an interval for each pixel, and a third opening adjacent to the first opening and the second opening by an interval along a second direction crossing the first direction, and wherein the spacer is at a crossing point of a first imaginary line extending in the first direction and passing between the first opening and the third opening and a second imaginary line extending in the second direction and passing between the first opening and the second opening.
US09508768B2
A method of manufacturing a semiconductor device, includes forming a trench in a semiconductor substrate having a first face and a second face by processing the first face of the semiconductor substrate, the trench including a first portion and a second portion located between the first portion and a plane including a first face, filling an insulator in the second portion such that a space remains in the first portion and the trench is closed, and forming a plurality of elements between the first face and the second face, wherein the space and the insulator form element isolation.
US09508765B2
A photodiode array detector used for detecting light which has undergone wavelength separation by a spectroscopic element, the photodiode array detector including: a light receiving element array wherein, taking a plurality of light receiving elements which detect light of the same wavelength range as one unit, a plurality of such units are arrayed in the direction of dispersion of said wavelength; and a charge accumulation time setting unit which sets different charge accumulation times for the plurality of light receiving elements within the one unit.
US09508764B2
The invention relates to a device for detecting electromagnetic radiation in the THz frequency range, comprising at least one transistor (FET1, FET2), which has a first electrode, a second electrode, a control electrode, and a channel between the first electrode and the second electrode, and comprising an antenna structure. An electrode is connected to the antenna structure such that an electromagnetic signal which lies in the THz-frequency range and which is received by the antenna structure (1) can be fed into the channel between electrodes and the control electrode is connected to an electrode via a capacitor and/or the control electrode and the first electrode or the control electrode and the second electrode have an intrinsic capacitor such that no AC voltage drop occurs between the control electrode and the first electrode or the second electrode.
US09508756B2
Disclosed is a display device including a seal material and a sealing material. The seal material surrounds a pixel portion and the sealing material overlaps with at least any of a driver circuit and a protective circuit. The pixel portion includes a planarization layer and an organic resin film each having an opening, an end portion of which is rounded. The pixel portion further includes a first electrode, a light-emitting member over the first electrode, and a second electrode over the light-emitting member. Part of the first electrode and part of the organic resin film are located in the opening of the planarization layer. Part of the light-emitting member and Part of the second electrode are located in the opening of the organic resin film.
US09508742B2
One object is to provide a new semiconductor device whose standby power is sufficiently reduced. The semiconductor device includes a first power supply terminal, a second power supply terminal, a switching transistor using an oxide semiconductor material and an integrated circuit. The first power supply terminal is electrically connected to one of a source terminal and a drain terminal of the switching transistor. The other of the source terminal and the drain terminal of the switching transistor is electrically connected to one terminal of the integrated circuit. The other terminal of the integrated circuit is electrically connected to the second power supply terminal.
US09508741B2
A method of forming fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device are described. The method includes forming a strained silicon-on-insulator (SSOI) layer in both a pFET region and an nFET region, etching the strained silicon layer, the insulator, and a portion of the bulk substrate in only the pFET region to expose the bulk substrate, epitaxially growing silicon (Si) from the bulk substrate in only the pFET region, and epitaxially growing additional semiconductor material on the Si in only the pFET region. The method also includes forming fins from the additional semiconductor material and a portion of the Si grown on the bulk substrate in the pFET region, and forming fins from the strained silicon layer and the insulator in the nFET region.
US09508734B2
A silicon-oxide-nitride-oxide-silicon (SONOS) device is disclosed. The SONOS device includes a substrate; a first oxide layer on the substrate; a silicon-rich trapping layer on the first oxide layer; a nitrogen-containing layer on the silicon-rich trapping layer; a silicon-rich oxide layer on the nitrogen-containing layer; and a polysilicon layer on the silicon-rich oxide layer.
US09508718B2
A device comprises a substrate comprising a first portion and a second portion separated by an isolation region, a first gate structure over the first portion, a first drain/source region and a second drain/source region in the first portion and on opposite sides of the first gate structure, wherein the first drain/source region and the second drain/source have concave surfaces, a second gate structure over the second portion and a third drain/source region and a fourth drain/source region in the second portion and on opposite sides of the second gate structure, wherein the third drain/source region and the fourth drain/source have the concave surfaces.
US09508710B2
A technology capable of suppressing a fluctuation in voltage in a diode region is provided. A resistance value between the emitter electrode and the lower body region is lower than a resistance value between the anode electrode and the lower anode region when the semiconductor device operates as a diode. A quantity of holes between the emitter electrode and the second barrier region is smaller than a quantity of holes between the anode electrode and the first barrier region.
US09508709B2
An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect transistor, a switch, and a capacitor are provided. The field-effect transistor includes a first gate and a second gate which overlap with each other with a channel formation region therebetween, and the threshold voltage of the field-effect transistor varies depending on the potential of the second gate. The switch has a function of determining whether electrical connection between one of a source and a drain of the field-effect transistor and the second gate of the field-effect transistor is established. The capacitor has a function of holding a voltage between the second gate of the field-effect transistor and the other of the source and the drain of the field-effect transistor.
US09508706B2
An input signal having a high level or a low level is input to a pad. A first protection element includes a first transistor configured as an N-channel MOSFET designed so as to withstand ESD. A second protection element includes a second transistor configured as a P-channel MOSFET designed so as to withstand ESD. A capacitance element is connected to a second line, and forms an RC filter together with a filter resistor. The capacitance element includes at least one from among a third transistor having the same device structure as that of the first transistor and a fourth transistor having the same device structure as that of the second transistor.
US09508702B2
A method for 3D device packaging utilizes through-substrate metal posts to mechanically and electrically bond two or more dice. The first die includes a set of access holes extending from a surface of the first die to a set of pads at a metal layer of the first die. The second die includes a set of metal posts. The first die and the second die are stacked such that each metal post extends from a surface of the second die toward a corresponding pad via a corresponding access hole. The first die and second die are mechanically and electrically bonded via solder joints formed between the metal posts and the corresponding pads.
US09508699B2
A semiconductor package includes an interposer, first and second semiconductor chips horizontally arranged over a first surface of the interposer, the second semiconductor chip being adjacent to the first semiconductor chip, and a thermal expansion reinforcing pattern disposed over a second surface of the interposer.
US09508678B2
A method of manufacturing a semiconductor device which improves the reliability of a semiconductor device. The method of manufacturing the semiconductor device includes the step of connecting a ball portion formed at the tip of a wire with a pad (electrode pad) of a semiconductor chip. The pad is comprised of an aluminum-based material and has a trench in its portion to be connected with the ball portion. The ball portion is comprised of a harder material than gold. The step of connecting the ball portion includes the step of applying ultrasonic waves to the ball portion.
US09508669B2
A semiconductor device that includes a bipolar transistor, wherein a third opening, through which a pillar bump and a second wiring line, which is electrically connected to an emitter layer, contact each other, is shifted in a longitudinal direction of the emitter layer away from a position at which the third opening would be directly above the emitter layer. The third opening is arranged, with respect to the emitter layer, such that an end portion of the emitter layer in the longitudinal direction of the emitter layer and the edge of the opening of the third opening are substantially aligned with each other.
US09508665B2
A method for insertion bonding and a device thus obtained are disclosed. In one aspect, the device includes a first substrate having a front main surface and at least one protrusion at the front main surface. The device includes a second substrate having a front main surface and at least one hole extending from the front main surface into the second substrate. The protrusion of the first substrate is inserted into the hole of the second substrate. The hole is formed in a shape wherein the width is reduced in the depth direction and wherein the width of at least a part of the hole is smaller than the width of the protrusion at the location of the metal portion thereof. The protrusion is deformed during insertion thereof in the hole to provide a bond between the part of the hole and the metal portion.
US09508651B2
A semiconductor device includes a semiconductor chip, a bump electrode, a molding portion, a redistribution layer and an outer connection electrode. The bump electrode is provided on an upper face of the semiconductor chip. The molding portion encapsulates an entire side face of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed. The redistribution layer is provided on an upper face of the molding portion and is electrically coupled to the semiconductor chip via the bump electrode. The outer connection electrode is provided on an upper face of the redistribution layer and is electrically coupled to the bump electrode via the redistribution layer.
US09508639B2
A package-in-substrate includes an exposed pad having a surface that is capable of contacting the outside; a semiconductor chip arranged on a surface opposite to the surface of the exposed pad; a molding resin for molding the semiconductor chip; and a lead frame extending from a side surface of the molding resin and having a leading end portion with a machined shape. The leading end portion of the lead frame is cut to have a cutting angel that is an acute angle formed by an extended straight line of the lead frame with respect to a top surface of a package.
US09508635B2
Methods of forming conductive jumper traces for semiconductor devices and packages. Substrate is provided having first, second and third trace lines formed thereon, where the first trace line is between the second and third trace lines. The first trace line can be isolated with a covering layer. A conductive layer can be formed between the second and third trace lines and over the first trace line by a depositing process followed by a heating process to alter the chemical properties of the conductive layer. The resulting conductive layer is able to conform to the covering layer and serve to provide electrical connection between the second and third trace lines.
US09508626B2
A semiconductor device has a thermally-conductive frame and interconnect structure formed over the frame. The interconnect structure has an electrical conduction path and thermal conduction path. A first semiconductor die is mounted to the electrical conduction path and thermal conduction path of the interconnect structure. A portion of a back surface of the first die is removed by grinding. An EMI shielding layer can be formed over the first die. The first die can be mounted in a recess of the thermally-conductive frame. An opening is formed in the thermally-conductive frame extending to the electrical conduction path of the interconnect structure. A second semiconductor die is mounted over the thermally-conductive frame opposite the first die. The second die is electrically connected to the interconnect structure using a bump disposed in the opening of the thermally-conductive frame.
US09508622B2
A semiconductor device and method for encapsulating the semiconductor device are provided. The method includes: forming a plurality of wire bonds on a surface of the semiconductor device by bonding each of a plurality of copper wires onto corresponding ones of a plurality of aluminum pads; applying a protective material around the plurality of wire bonds, the protective material having a first pH; and encapsulating at least a portion of the semiconductor device and the protective material with an encapsulating material having a second pH, wherein the first pH of the protective material is for neutralizing the second pH of the encapsulating material around the plurality of wire bonds.
US09508614B2
A method for aligning a chip onto a substrate is disclosed. The method includes, depositing a ferrofluid, onto a substrate that has one or more pads that electrically couple to a semiconductor layer. The method can include a chip with solder balls electrically coupled to the logic elements of the chip, which can be placed onto the deposited ferrofluid, where the chip is supported on the ferrofluid, in a substantially coplanar orientation to the substrate. The method can include determining if the chip is misaligned from a desired location on the substrate. The method can include adjusting the current location of the chip in response to determining that the solder balls of the chip are misaligned from the desired location on the pads of the substrate, until the chip is aligned in the desired location.
US09508612B2
Methods and systems for accurate arc detection in semiconductor manufacturing tools are disclosed. Such methods and systems provide real-time arc detection and near real-time notification for corrective actions during a semiconductor manufacturing process. Such methods and systems utilize data with high sample rate and wavelet analysis to provide for more accurate arc detection, which leads to more effective and cost efficient semiconductor manufacturing operations.
US09508607B2
Some implementations provide a package that includes a first die and a second die adjacent to the first die. The second die is capable of heating the first die. The package also includes a leakage sensor configured to measure a leakage current of the first die. The package also includes a thermal management unit coupled to the leakage sensor. The thermal management unit configured to control a temperature of the first die based on the leakage current of the first die.
US09508602B2
Semiconductor structures and methods of fabrication are provided for, for instance, inhibiting diffusion of active dopant within a semiconductor material. A diffusion-suppressing dopant is implanted via, an implanting process under controlled temperature, into a semiconductor material of a semiconductor structure to define a diffusion-suppressed region within the semiconductor material. One or more active regions are established within the diffusion-suppressed region of the semiconductor structure by, for example, implanting an active dopant into the semiconductor material. The implanting of the diffusion-suppressing dopant facilitates inhibiting diffusion of the active dopant within the diffusion-suppressed region.
US09508598B2
To enhance reliability and performance of a semiconductor device that has a fully-depleted SOI transistor, while a width of an offset spacer formed on side walls of a gate electrode is configured to be larger than or equal to a thickness of a semiconductor layer and smaller than or equal to a thickness of a sum total of a thickness of the semiconductor layer and a thickness of an insulation film, an impurity is ion-implanted into the semiconductor layer that is not covered by the gate electrode and the offset spacer. Thus, an extension layer formed by ion implantation of an impurity is kept from entering into a channel from a position lower than the end part of the gate electrode.
US09508591B2
Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
US09508589B2
Methods of fabricating middle of line (MOL) layers and devices including MOL layers. A method in accordance with an aspect of the present disclosure includes depositing a hard mask across active contacts to terminals of semiconductor devices of a semiconductor substrate. Such a method also includes patterning the hard mask to selectively expose some of the active contacts and selectively insulate some of the active contacts. The method also includes depositing a conductive material on the patterned hard mask and the exposed active contacts to couple the exposed active contacts to each other over an active area of the semiconductor devices.
US09508584B2
Embodiments described herein generally relate to an electrostatic chuck (ESC). The ESC may contain a first plurality of electrodes adapted to electrostatically couple a substrate to the ESC and a second plurality of electrodes adapted to electrostatically couple the ESC to a substrate support. Instead of being integrally disposed within the substrate support, the ESC may be easily removed from the substrate support and removed from a chamber for maintenance or replacement purposes.
US09508577B2
A semiconductor manufacturing apparatus may include: a pickup unit configured to pick up a chip in a first region of the semiconductor manufacturing apparatus; a bonding head configured to receive the picked-up chip and configured to move from the first region to a top of a circuit board in a second region of the semiconductor manufacturing apparatus; and/or an optical unit configured to detect a bonding position on the circuit board while moving from the first region to the second region. A semiconductor manufacturing apparatus may include: a bonding head including a heater for heating a chip and bonding the chip onto a circuit board; and/or a cooling block, adjacent to the heater, through which cooling liquid flows. The cooling liquid may be removed from the cooling block while the heater generates heat. The cooling liquid may be supplied to the cooling block while the heater is cooled.
US09508574B2
According to an embodiment of the present disclosure, a process liquid supply apparatus operating method is provided. The method includes filling a filter unit with a process liquid from an upstream side of the filter unit to a downstream side of the filter unit after newly mounting or replacing the filter unit and repeating a depressurization filtering process and a pressurization filtering process for a predetermined number of times. The depressurization filtering process depressurizes the process liquid in the downstream side of the filter unit and thereby allows the process liquid to permeate through the filter unit. The pressurization filtering process pressurizes the process liquid from the upstream side of the filter unit and thereby allows the process liquid to permeate through the filter unit.
US09508572B2
A boding device includes a light guiding part that guides laser beam oscillated from a laser oscillator, a bonding head that heats a chip with the laser beam, and a bonding head moving part that moves the bonding head between a supply position and a bonding position. The laser oscillator is separated from the bonding head. The light guiding part includes an irradiation barrel that is provided in the vicinity of the bonding position and, a shutter part that is provided in the irradiation barrel, and a light receiving part that is provided in the bonding head and guides the laser beam to the chip. When the bonding head moving part moves the bonding head to the bonding position, the shutter part is opened so that the laser beam from the irradiation barrel is guided to the bonding head through the light receiving part.
US09508568B2
A special mode has a second rinsing process which supplies a rinsing liquid to a substrate while holding and rotating the substrate with a spin chuck under operating conditions different from those in a first rinsing process in a normal mode. In the second rinsing process, a processing cup is cleaned with the rinsing liquid flown off from the rotating substrate. In the second rinsing process in which the substrate is held by the spin chuck, the rinsing liquid flown off from the substrate is less prone to collide with chuck members. The provision of a mechanism designed specifically for the cleaning of the cup is not required in the special mode. The special mode is a mode executable when a substrate is present inside a chamber, and can be executed in the middle of lot processing.
US09508566B2
Embodiments of the invention include a method for shaping a flexible integrated circuit to a curvature and the resulting structure. A flexible circuit is provided. An epoxy resin and amine composition is deposited on the flexible integrated circuit. The deposited epoxy resin and amine composition is B-staged. The flexible integrated circuit is placed within a mold of a curvature. The B-staged epoxy resin and amine composition is cured subsequent to placing the flexible integrated circuit within the mold of the curvature.
US09508565B2
The semiconductor package according to an exemplary embodiment includes: a substrate having a plurality of circuit layers and connection pads which are provided between a plurality of insulating layers; a plated tail part of which one end is electrically connected to the connection pad; a dicing part provided in contact with the other end of the plated tail part; a molded part provided on the substrate; and molded part vias provided on the connection pads and penetrating through the molded part.
US09508564B2
A plurality of semiconductor element is formed on a substrate. A plurality of sealing windows and a support portion supporting the plurality of sealing windows are formed on a SOI substrate. The SOI substrate is pressured against the substrate by using a pressurizing member and the plurality of sealing windows of the SOI substrate is bonded to the substrate via a low melting point glass member arranged around the plurality of semiconductor elements. The support portion is separated from the plurality of sealing windows bonded to the substrate.
US09508548B2
A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.
US09508546B2
A method of manufacturing a semiconductor device is disclosed. The method includes (a) loading a substrate into a process chamber; (b) processing the substrate by supplying a process gas into the process chamber via a shower head disposed above the process chamber and including a buffer chamber; (c) unloading the substrate from the process chamber; and (d) cleaning the buffer chamber and the process chamber after performing the step (c), wherein the step (d) comprises: (d-1) cleaning the buffer chamber by a plasma generation from a cleaning gas in the buffer chamber by a plasma generation unit including a plasma generation region switching unit; and (d-2) cleaning the process chamber by switching the plasma generation from the cleaning gas in the buffer chamber to a plasma generation from the cleaning gas in the process chamber by the plasma generation region switching unit.
US09508539B2
A glow discharge mass spectrometry device and method, the device including a glow discharge lamp (1), gas flow-injection elements, the glow discharge lamp being suitable for forming an ablation plasma in the presence of a plasma gas, and a mass spectrometer. The device further includes heating elements (30, 31) suitable for heating a gas flow (38) upstream of a cell (2), the gas flow-injection elements being suitable for injecting into the glow discharge cell a gas flow (38) heated to a temperature T for a duration D, and pumping elements (7, 27) being designed to pump a flow of gaseous species (17, 37) out of the cell for the duration D, so as to decontaminate the surface of the sample (4) and/or the inner walls of the glow discharge cell (2) before an ablation plasma (5) is ignited.
US09508535B2
An ion mobility spectrometer having an ion source for generating ions; an ion detector for recording ions, and a number of substantially flat diaphragm electrodes arranged substantially perpendicular to a straight system axis that passes through the apertures in said diaphragms, with the diaphragms being arranged in a series of cells with each cell including an entrances and an exit diaphragm and a short region in between. The exit diaphragm of one cell is identical to the entrance diaphragm of the next cell, and the cells of said ion mobility spectrometer are grouped into three parts: an ion-beam forming region, an ion analyzing region, and a decelerating ion gate.
US09508532B2
A magnetron plasma apparatus boosted by hollow cathode plasma includes at least one electrically connected pair of a first hollow cathode plate and a second hollow cathode plate placed opposite to each other at a separation distance of at least 0.1 mm and having an opening following an outer edge of a sputter erosion zone on a magnetron target so that a magnetron magnetic field forms a perpendicular magnetic component inside a hollow cathode slit between plates and, wherein the plates and are connected to a first electric power generator together with the magnetron target to generate a magnetically enhanced hollow cathode plasma in at least one of a first working gas distributed in the hollow cathode slit and a second working gas admitted outside the slit in contact with a magnetron plasma generated in at least one of the first working gas and the second working gas.
US09508531B2
The method of the present invention is related to a technique of efficiently purging source gases remaining on a substrate and improving in-plane uniformity of a substrate. The method of the present invention includes forming a thin film on a substrate accommodated in a process chamber by (a) supplying a source gas into the process chamber, and (b) supplying an inert gas into the process chamber while alternately increasing and decreasing a flow rate of the inert gas supplied into the process chamber and exhausting the source gas and the inert gas from the process chamber.
US09508527B2
This charged particle beam device irradiates a primary charged particle beam generated from a charged particle microscope onto a sample arranged on a light-emitting member that makes up at least a part of a sample base, and, in addition to obtaining charged particle microscope images by the light-emitting member detecting charged particles transmitted through or scattered inside the sample, obtains optical microscope images by means of an optical microscope while the sample is still arranged on the sample platform.
US09508523B2
This invention provides a source of x-ray flux in which x-rays are produced by e-beams impacting the inner walls of holes or channels formed in a metal anode such that most of the electrons reaching the channel impact an upper portion of said channel. A portion of the electrons from this primary impact will generate x-rays. Most of the electrons scatter but they continue to ricochet down the channel, most of them generating x-rays, until the beam is spent. A single channel source of high power efficiency and high power level x-rays may be made in this way, or the source can be of an array of such channels, to produce parallel collimated flux beams of x-rays.
US09508518B2
A first battery connecting end, an alternator connecting end and a second battery connecting end of a circuit body are located at an upper surface portion of a unit body.
US09508503B2
Embodiments of the disclosure optimize yield of a product having one or more switch assemblies and improve impact robustness of the product without sacrificing tactile feel. Based on failure limits of a gap in the switch assembly during manufacturing, a single size for a shim is calculated. The shim is selectively inserted into the switch assembly based on the gap to maximize the switch assembly yield while minimizing cost. In some examples, a bracket is designed for the switch assemblies. The bracket has datum surfaces in three dimensions and a beam tuned to absorb energy during an impact event to prevent switch failure.
US09508491B2
The invention is relates to a method for manufacturing a capacitor. The method has the following steps: a) providing an electrode body made of an electrode material, wherein a dielectric at least partially covers a surface of the electrode material, to obtain an anode body; b) introducing a dispersion, which contains particles of an electrically conductive polymer with a particle size (d50) of 70 nm and less and a dispersing agent, into at least a part of the anode body; c) at least partial removing the dispersing agent, to obtain a capacitor body; and d) introducing, into the capacitor body, a polyalkylene glycol or a polyalkylene glycol derivative or a combination of at least two thereof as an impregnating agent.
US09508490B2
An electronic component and method for manufacture thereof is disclosed. A plurality of electrodes are positioned in stacked relation to form an electrode stack. The stack may include as few as two electrodes, but more may be used depending on the number of subcomponents desired. Spacing between adjacent electrodes is determined by removable spacers during fabrication. The resulting space between adjacent electrodes is substantially filled with gaseous matter, which may be an actual gaseous fill, air, or a reduced pressure gas formed through evacuation of the space. Further, adjacent electrodes are bonded together to maintain the spacing. A casing is formed to encapsulate the stack, with first and second conducting surfaces remaining exposed outside the casing. The first conducting surface is electrically coupled to a first of the electrodes, and the second conducting surface is electrically coupled to a second of the electrodes.
US09508487B2
This disclosure provides systems, methods, and apparatus for the limiting of voltage in wireless power receivers. In one aspect, an apparatus includes a power transfer component configured to receive power wirelessly from a transmitter. The apparatus further includes a circuit coupled to the power transfer component and configured to reduce a received voltage when activated. The apparatus further includes a controller configured to activate the circuit when the received voltage reaches a first threshold value and configured to deactivate the circuit when the received voltage reaches a second threshold value. The apparatus further includes an antenna configured to generate a signal to the transmitter that signals to the transmitter that the received voltage reached the first threshold value.
US09508486B2
Embodiments of a high temperature electromagnetic coil assembly are provided, as are embodiments of a method for fabricating such a high temperature electromagnetic coil assembly. In one embodiment, the high temperature electromagnetic coil assembly includes a coiled anodized aluminum wire and an electrically-insulative, high thermal expansion ceramic body in which the coiled anodized aluminum wire is embedded. The electrically-insulative, high thermal expansion ceramic body has a coefficient of thermal expansion greater than 10 parts per million per degree Celsius and less than the coefficient of thermal expansion of the coiled anodized aluminum wire.
US09508482B2
U-shaped cores and fasteners are embedded in resin members, and brackets provided at respective ends of the fasteners protrude from the resin members. By fixing the brackets and a casing with screws, a reactor main body and the casing are fixed together. Openings formed by a partition wall that suppresses a direct application of a resin flowing from resin-filling portions to the fasteners are provided between the respective fasteners and the respective resin-filling portions. A protrusion extending in an opposite direction to a core and in parallel with the partition wall is provided between the resin-filling portions and the partition wall. The resin flowing from the resin-filling portion flows in between a core upper face and the fastener, and between a fastener surface located behind the partition wall and the internal surface of a die.
US09508478B1
A diamagnetic levitation system for levitating users to a levitation surface upon which they may engage in sports and other activities under relatively weightless conditions in a dome-shaped structure. Superconducting magnet segments are connected in series to form a superconducting magnet segment assembly. A plurality of these superconducting magnet segment assemblies form the diamagnetic levitation system. The diamagnetic levitation system not only generates the levitation surface to which players or other users are levitated but also confines them within the boundaries of the levitation surface. The magnetic field strength of the diamagnetic levitation system is self-terminating so that spectators viewing the players are not affected by the levitating magnetic field.
US09508475B2
The present invention provides a magnetic multilayer pigment flake and a magnetic coating composition that are relatively safe for human health and the environment. The pigment flake includes one or more magnetic layers of a magnetic alloy and one or more dielectric layers of a dielectric material. The magnetic alloy is an iron-chromium alloy or an iron-chromium-aluminum alloy, having a substantially nickel-free composition. The coating composition includes a plurality of the pigment flakes disposed in a binder medium.
US09508473B2
[Object] To provide a chip resistor with which laser irradiation requires no extremely high positional accuracy, and a plating layer provided on a base and adjacent to a resistor element can be connected to an external conductive layer. [Solution] A chip resistor includes a base 1, a first principal surface electrode 21, a second principal surface electrode spaced apart from the first principal surface electrode 21 in a first direction X1, a resistor element 4 in contact with the first principal surface electrode 21 and the second principal surface electrode 31, an overcoat 6 covering the resistor element 4, the first principal surface electrode 21 and the second principal surface electrode, a first auxiliary electrode 25 covering the first principal surface electrode 21 and the overcoat 6, and a first plating electrode 27 covering the first auxiliary electrode 25. The first auxiliary electrode 25 includes a portion 259 offset from the first principal surface electrode 21 in the first direction X1.
US09508469B2
A peelable superconductive conductor comprising a superconductive conductor including a substrate and a superconducting layer which is formed on one principal surface of the substrate. The peelable superconductive conductor can further comprise a peelable carrier body, which is formed on a principal surface of the superconductive conductor on an opposite side of the surface on which the superconducting layer is formed.
US09508466B2
A high-frequency electric wire is provided with a conductor which formed by compressing multiple wire strands, each of which is obtained by coating an outside of a wire rod made of insulating resin with a metal layer, and a sheath provided on the conductor. Each of the wire strands of the conductor is compressed in such a way that a deformation ratio of the wire strand exceeds 0% and is 20% or less. The compression is performed, for example, during bundling and sheathing of the multiple wire strands.
US09508462B2
A Sn-coated copper alloy strip including a surface coating layer containing a Ni layer, a Cu—Sn intermetallic compound layer, and a Sn layer formed in this order over the surface of a base material containing a copper alloy strip, in which an average thickness of the Ni layer is from 0.1 to 3.0 μm, an average thickness of the Cu—Sn intermetallic compound layer is from 0.02 to 3.0 μm, an average thickness of the Sn layer is from 0.01 to 5.0 μm, and the Cu—Sn intermetallic compound layer contains only an η-phase or the η-phase and an ε-phase.
US09508452B2
A partial chip and a system including the partial chip are provided. The partial chip includes a memory cell array and a signal control circuit. The memory cell array includes a pass region and a fail region. The signal control circuit is configured to generate second data corresponding to first data to be output from the fail region.
US09508448B2
A memory element having a novel structure and a signal processing circuit including the memory element are provided. A first circuit, including a first transistor and a second transistor, and a second circuit, including a third transistor and a fourth transistor, are included. A first signal potential and a second signal potential, each corresponding to an input signal, are respectively input to a gate of the second transistor via the first transistor in an on state and to a gate of the fourth transistor via the third transistor in an on state. After that, the first transistor and the third transistor are turned off. The input signal is read out using both the states of the second transistor and the fourth transistor. A transistor including an oxide semiconductor in which a channel is formed can be used for the first transistor and the third transistor.
US09508444B2
A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line.
US09508438B2
An embodiment of the invention may provide a semiconductor memory device including a memory cell array including a plurality of memory cells, a peripheral circuit unit configured to perform a program operation with respect to a memory cell selected from the plurality of memory cells, wherein first to third program voltage applying operations and first to third verifying operations are alternatively performed, and a control logic configured to control the peripheral circuit unit to perform the first to third program voltage applying operations and the first to third verifying operations and to increase a second program voltage applied during the second program voltage applying operation more than a first program voltage applied during the first program applying operation by a first step voltage and a third program voltage applied during the third program voltage applying operation more than the second program voltage by a second step voltage.
US09508435B1
A writing method for a resistive memory apparatus is provided. In the method, logic data is received, and a corresponding selection memory cell is selected. A logic level of the logic data is determined. When the logic data is at a first logic level, a RESET pulse is provided to the selection memory cell and then a SET pulse smaller than a reference write current and having a near-rectangular pulse width is provided to the selection memory cell during a writing period. When the logic data is at a second logic level, the RESET pulse is provided to the selection memory cell and then a SET pulse larger than the reference write current and having the near-rectangular pulse width is provided to the selection memory cell during the writing period.
US09508434B2
A non-volatile memory including a plurality of elementary cells, each cell including: a first programmable-resistance storage element connected between first and second nodes of the cell; a first access transistor coupling the second node to a third node of the cell; and a second access transistor coupling the second node to a fourth node of the cell.
US09508432B2
This semiconductor device is provided with: a variable resistance first switch (103), which has a first terminal and a second terminal, and which has the resistance value thereof varied when an applied voltage exceeds a reference value; a variable resistance second switch (104), which has a third terminal and a fourth terminal, and which forms an intermediate node (105) by having the third terminal connected to the second terminal, and has the resistance state thereof varied when an applied voltage exceeds a reference value; first wiring (101) connected to the first terminal; second wiring (102), which is connected to the fourth terminal, and which extends in the direction intersecting the first wiring (101) in a planar view; a first selection switch element (106) connected to the first wiring (101); and a second selection switch element (107) connected to the second wiring (102).
US09508429B2
A vertical type semiconductor device and a fabrication method thereof are provided. The vertical type semiconductor device includes a pillar structure having a stacking structure of a conductive layer and a data storage material and formed on a common source region, and a gate electrode formed to surround the data storage material of the pillar structure.
US09508427B2
Some embodiments include apparatuses and methods having first conductive lines, second conductive lines, a memory array including memory cells, each of the memory cells coupled between one of the first conductive lines and one of the second conductive lines. At least one of such apparatuses and methods can include a module configured to cause a first current from a first current source and a second current from a second current source to flow through a selected memory cell among the memory cells during an operation of storing information in the selected memory cell. Other embodiments including additional apparatuses and methods are described.
US09508426B2
Methods, systems, and devices related to memory, including read or write performance of a phase change memory, are described. A plurality of memory cells of a memory array may be read. A total number of read errors resulting from the read operation of the plurality of memory cells may be determined, and reference read currents may be adjusted if the total number of read errors exceeds an error threshold. In some examples, adjusting reference read currents includes reading a reference memory cell, determining a current shift for the reference memory cell, and adjusting read currents for other memory cells of the memory array by a current delta based at least in part on the current shift.
US09508422B2
A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
US09508420B1
Approaches for a write assist circuit are provided. The write assist circuit includes a plurality of binary weighted boost capacitors which each contain a first node coupled to a bitline and a second node connected to a corresponding boost enabling transistor, and a plurality of boost enabling transistors which each contain a gate connected to a boost control enable signal for controlling a corresponding binary weighted boost capacitor. The boost control enable signal of each of the plurality of boost enabling transistors is controlled by encoded values based on a power supply level.
US09508419B2
Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.
US09508418B1
A semiconductor device may include: a command decoder configured to decode a clock signal, a chip selection signal, and a command address, and output an active write signal, an active read signal, and a precharge signal indicating a write operation or a read operation after completion of an active operation; a row controller configured to output a bank active signal for controlling an active operation of a bank in response to the active write signal, the active read signal, and the precharge signal, and output an active write flag signal or an active read flag signal for performing the write operation or the read operation; and a column controller configured to output a control signal for controlling a column active operation to the bank in response to the active write flag signal, the active read flag signal, a write command signal, a read command signal, and the precharge signal.
US09508417B2
Apparatuses and methods for controlling timing circuit locking and/or latency during a change in clock frequency (e.g. gear down mode) are described herein. An example apparatus may include a timing circuit. The timing circuit may be configured to provide a clock signal to the forward path, adjust a rate of the clock signal responsive to receipt of a command to adjust the rate of the clock signal, select a feedback clock signal responsive to a loop delay of the timing circuit, and provide a control signal to an adjustable delay circuit of the forward path circuit. Another example apparatus may include a forward path configured to delay a signal based at least in part on a loop delay and a latency value, and a latency control circuit configured to provide an adjusted latency value as the latency value responsive to receipt of a command, wherein the forward path is configured to operate at least in part at an adjusted clock rate responsive to receipt of the command.
US09508412B2
A semiconductor memory apparatus includes a bank; a temperature sensor configured to generate a temperature voltage of which voltage level is changed according to a temperature variation of the bank; and a timing control block configured to control a timing of a signal to be inputted to the bank, according to the voltage level of the temperature voltage.
US09508410B1
A semiconductor device includes a control signal generating unit, a first address generating unit, and a second address generating unit. The control signal generating unit generates a read/write control signal and a selection control signal in response to an active signal. The first address generating unit generates a first address signal in response to the selection control signal and a second address signal. The second address generating unit generates the second address signal in response to the read/write control signal and the first address signal.
US09508403B2
A semiconductor device may include a first channel configured to output a first rising clock, a first falling clock, first rising data, and first falling data. The semiconductor device may include a second channel configured to output a second rising clock, a second falling clock, second rising data, and second falling data. The semiconductor device may include an I/O control unit configured to receive the first rising clock, the first falling clock, the first rising data, and the first falling data, generate output data, and externally output the output data through a pad unit or receive the second rising clock, the second falling clock, the second rising data, and the second falling data, generate the output data, and externally output the output data through the pad unit.
US09508399B1
In some examples, a method includes determining, by a processor of a controller of a data storage device, that a voltage level of a capacitor in the data storage device is above a threshold voltage value, wherein the data storage device includes a capacitor circuit, and wherein the capacitor circuit includes the capacitor. The method further includes controlling, by the processor, the capacitor circuit to cause the capacitor to provide power to circuitry associated with memory devices of the data storage device along with power provided by a host device operably connected to the data storage device.
US09508398B1
A semiconductor memory device includes a voltage generation unit suitable for selecting one of the voltages which are supplied to a first and a second source voltage terminals, as a source voltage based on a driving mode signal, and generating a bit line precharge voltage by dividing the source voltage according to a resistance ratio determined based on the driving mode signal; a sense amplifier driving unit suitable for receiving the bit line precharge voltage based on a bit line precharge signal and a sense amplifier control signal, and providing a driving voltage through a pull-up power line and a pull-down power line; and a bit line sense amplifier suitable for sensing and amplifying data of a bit line pair by using the driving voltage supplied through the pull-up power line and the pull-down power line.
US09508396B2
An array structure of a single-poly nonvolatile memory includes a first and a second MTP sections, a first and a second OTP sections. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The second MTP section is connected to a second word line, a second source line and shares the first erase line and the plurality of bit lines with the first MTP section. The first OTP section is connected to a third word line and shares the first source line and the plurality of bit lines with the first MTP section. The second OTP section is connected to a fourth word line, a third source line, and shares the plurality of bit lines with the first MTP section, the second MTP section and the third OTP section.
US09508394B2
An integrated circuit system comprising a first chip including a first period signal generation unit configured to generate a first period signal, transmit a first signal applied from a circuit outside of the integrated circuit system to a second chip, and transmit a second signal transmitted from the second chip to the circuit outside of the integrated circuit system, and the second chip including a second period signal generation unit configured to generate a second period signal, a code generation unit configured to generate codes corresponding to a difference between periods of the first period signal and the second period signal, and a delay unit configured to delay the second signal by using a delay value that is changed according to the codes.
US09508388B2
The present invention relates to a method for preparing presentation of recorded motion video. The method preparing and sending a request for recorded video that originates from a specific video source, receiving a video information message including data relating to characteristics of a plurality of motion video recordings captured by the video source, wherein the received characteristics of each motion video recording includes a recording identity, a video quality value, a media address, an indication of start time and end time for the recording, and generating a motion video play scheme based at least on said video quality value, said indication of start time, and said indication of end time for each motion video recording.
US09508382B2
A method and apparatus for performing a read/write process on a recording medium having a defect, the method including determining an area of a recording medium, in which a defect, greater than a first set threshold, occurring in units of tracks, to be a massive defective area; adjusting a first parameter representing a logical track length, based on a size of a defect occurring in each track included in the massive defective area; and performing the read/write process on the recording medium by using the adjusted first parameter.
US09508377B2
A hologram recording and reproducing device and an angular multiplexing recording and reproducing method capable of detecting an angular error signal for which, in a two-beam angle multiplexing method, high-speed reproducing can be achieved with a superior recovered signal. A branch element branches a light beam, emitted from a light source, into a signal light and a reference light. Angle-variable elements modify the incident angle of the reference light that is incident to the optical information recording medium. A spatial light modulator adds information to the signal light; and an objective lens radiates the signal light to the optical information recording medium. An imaging element detects diffracted light generated from a recording region when the reference light is radiated upon the optical information recording medium; a detection system detects at least two angular error signals for controlling the angle-variable elements; and switching is performed between the two angular error signals.
US09508376B2
Methods and apparatus for archival storage of an image are disclosed. The image may be separated into a plurality of bit plane images. The plurality of bit plane images may be written separately onto digital optical tape.
US09508372B1
A method and system provide a shingle magnetic write transducer. The transducer has an air-bearing surface (ABS) and includes a main pole and at least one coil. The coil(s) are configured to energize the main pole. The main pole includes a leading surface, a trailing surface, and a plurality of sides between the leading surface and the trailing surface. At least one of the plurality of sides form a sidewall angle with a down track direction. The sidewall angle is less than thirteen degrees and is at least zero degrees. In some aspects, the sidewall angle is less than a maximum skew angle for the data storage system.
US09508363B1
A method provides a magnetic transducer having an air-bearing surface (ABS) location. An intermediate layer having a substantially flat bottom surface is provided. A trench is formed in the intermediate layer. The trench is wider in yoke region than in the pole tip region. The trench has a first depth in the yoke region and a second depth less than the first depth in the pole tip region. A portion of the intermediate layer is at the bottom of the trench at the ABS location. A nonmagnetic layer is provided. The nonmagnetic layer fills part of the trench in the pole tip region such that the trench has a third depth less than the second depth at the ABS location. A main pole is provided. The main pole has a leading bevel adjacent to nonmagnetic layer in the portion of the pole tip region of the trench.
US09508362B2
A storage device includes a controller that implements an interlaced magnetic recording scheme with prioritized random access. According to one implementation, a controller is configured to write data at a first linear density to alternating data tracks and write data at a second linear density to one or more data tracks interlaced with the alternating data tracks.
US09508358B2
Noise reduction system with remote noise detector The present invention relates to a noise reduction system with at least one remote noise detector placed close to at least one noise source, which transmits relevant information to a primary device where it is used for noise reduction. Thereby, acoustic signal enhancement can be achieved via the at least one remote noise detector in that a noise estimate is transmitted to controller for noise reduction in the signal obtained from a primary source.
US09508357B1
Apparatus for optimizing beamformers for echo control comprises microphones to receive acoustic signals, echo cancellers (ECs) respectively coupled to the microphones to adaptively cancel echo in the acoustic signals and to generate EC-acoustic signals, and a first fixed beamformer coupled to the ECs to receive the EC-acoustic signals. The null of the first beamformer is steered in a direction of a first environmental noise source that is determined offline by exciting the ECs with normal speech signals and audio playback signals to cause the ECs to generate test EC-acoustic signals, and selecting the first environmental noise source based on loudness weighted centroids of noise in the test EC-acoustic signals. Apparatus may also include a residual echo suppressor coupled to the first fixed beamformer to perform echo suppression on output of the first fixed beamformer and to generate clean signal. Other embodiments are also described.
US09508356B2
An encoding device is provided for improving decoded signal quality. A local search unit conducts a local search on a plurality of sub-bands generated by dividing spectrum data, and calculates lattice vectors for the spectra in the plurality of sub-bands. A multi-rate indexing unit uses the lattice vectors to perform multi-rate indexing on each of the sub-bands, and generates indexing information showing the results thereof. A band selection unit determines certain sub-bands from amongst the plurality of sub-bands in a plurality of encoding layers as perceptually important sub-band groups, where these are: within a selection range of sub-bands wherein the total number of encoding bits allocated to each of the plurality of sub-bands in the indexing information is equal to or less than an already set value, and within a sub-band selection range with the highest total energy of each of the plurality of sub-bands.
US09508353B2
Provided are a method and apparatus for encoding and decoding a stereo signal or a multi-channel signal. According to the method and apparatus, a stereo signal or a multi-channel signal can be encoded and/or decoded by generating parameters based on a mono signal.
US09508352B2
An audio coding device that performs predictive coding on a third-channel signal included in a plurality of channels in an audio signal according to a first-channel signal and a second-channel signal, which are included in the plurality of channels, and to a plurality of channel prediction coefficients included in a coding book, the device includes a processor; and a memory which stores a plurality of instructions, which when executed by the processor, cause the processor to execute, selecting channel prediction coefficients corresponding to the first-channel signal and the second-channel signal so that an error, which is determined by a difference between the third-channel signal before predictive coding and the third-channel signal after predictive coding, is minimized; and controlling the first-channel signal or the second-channel signal so that the error is further reduced.
US09508349B2
Methods, systems, and terminal devices for transmitting information are provided. An exemplary system includes a sending end and at least one receiving end. The sending end is configured to obtain audio data to be transmitted, encode the obtained audio data according to an M-bit unit length, and use a pre-set cross-platform audio interface to control an audio outputting device of the sending end to send the encoded audio data to the at least one receiving end. The M-bit unit length is an encoding length corresponding to each frequency of a number N of frequencies, N is greater than or equal to 2, and M is greater than 0. The at least one receiving end is configured to use the pre-set cross-platform audio interface to control an audio inputting device of the at least one receiving end to receive the encoded audio data.
US09508345B1
Provided are methods and systems for continuous voice sensing. An example method allows for detecting and buffering, by a first module, a key phrase in an acoustic signal. Responsive to the detection, the method includes sending an interrupt to a second module and switching the first module to an omnidirectional microphone mode. Upon receiving the interrupt, the second module is operable to boot up from a low power mode to an operational mode. While the second module is booting up, the first module is operable to continue to buffer a clean speech output generated from an acoustic signal captured by at least one omnidirectional microphone. After the second module is booted, an indication may be sent to the first module that the second module is ready to exchange data through a fast connection. Upon receiving the indication, the buffered clean speech output may be sent to the second module.
US09508342B2
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, receiving audio data; determining that an initial portion of the audio data corresponds to an initial portion of a hotword; in response to determining that the initial portion of the audio data corresponds to the initial portion of the hotword, selecting, from among a set of one or more actions that are performed when the entire hotword is detected, a subset of the one or more actions; and causing one or more actions of the subset to be performed.
US09508340B2
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for recognizing keywords using a long short term memory neural network. One of the methods includes receiving, by a device for each of multiple variable length enrollment audio signals, a respective plurality of enrollment feature vectors that represent features of the respective variable length enrollment audio signal, processing each of the plurality of enrollment feature vectors using a long short term memory (LSTM) neural network to generate a respective enrollment LSTM output vector for each enrollment feature vector, and generating, for the respective variable length enrollment audio signal, a template fixed length representation for use in determining whether another audio signal encodes another spoken utterance of the enrollment phrase by combining at most a quantity k of the enrollment LSTM output vectors for the enrollment audio signal.
US09508337B2
A fume extractor hood is disclosed, comprising a box with a motor-fan assembly and a muffler module comprising a bearing frame defining an air extraction conduit with axis (A), an active noise suppression system comprising at least one electro-acoustic transducer and at least two microphones, a passive noise suppression system comprising a sound absorbent material. Said muffler module comprises at least two electro-acoustic transducers connected to the walls of said bearing frame, in opposite positions, in such manner to leave the central part of said conduit free. The sound beams coming from said at least two electro-acoustic transducers are mutually combined, obtaining a resulting sound beam that can be directed towards a preferred direction by means of beam forming algorithms.
US09508333B2
A magnetoelectric pickup device for use with a stringed musical instrument combines magnetostriction and the piezoelectric effect to detect a combination of magnetic field oscillations produced by a vibrating ferromagnetic string and acoustic vibrations from the body of the instrument itself. The result is a sound reproduction that preserves the natural acoustic timbre of the instrument.
US09508330B2
Embodiments of the invention include storing musical elements in a database and processing performance data, where the musical elements including a plurality of reference accent pattern data and a plurality of reference system pattern data. Processing performance data can include receiving input data corresponding to a musical performance, determining an accent pattern for the musical performance, matching the accent pattern data to one or more reference accent pattern data in the database, and selecting one of the matching reference accent patterns. Processing performance data further includes receiving input corresponding to a selection of a musical style, one or more musical performance parameters, and generating a musical accompaniment based on the processed performance data, the selected musical style, and the selected one or more musical performance.
US09508328B1
A digital sound effect apparatus including a force sensing resistor, a processor, and a digital potentiometer. The digital sound effect apparatus may also include one or more inputs and/or interfaces, one or more power sources, and one or more power switches. The force sensing resistor outputs a voltage according to a user's variable force or other input. The processor generates a signal according to a function or look-up table with the voltage as an input. The digital potentiometer outputs a resistance or other electronic characteristic to generate a sound effect according to the user's variable force. The function or look-up table may be changed or modified via the one or more inputs and/or interfaces.
US09508327B2
A pitch adjustment device for selectively adjusting the pitch of at least one of a plurality of strings on a stringed musical instrument. The device comprises a support frame configured to be mounted onto the stringed musical instrument. A string puller is rotatably coupled to the support frame. A string support is coupled to the string puller. The string support is adjustably positionable along the string puller to selectively position the string support on the string puller in alignment with each of the strings one at a time. The string support also has a string retainer for securing a string. A lever is coupled to the string puller such that pivoting the lever rotates the string puller and the string support relative to the frame about the first axis. The lever has a normal position and an actuated position in which the lever is pivoted to adjust the pitch.
US09508325B2
A white key of a keyboard instrument includes: an upper wall elongated in a front and rear direction; and a pair of side walls extending downward respectively from right and left edges of the upper wall and each elongated in the front and rear direction. The upper wall and the pair of side walls define an inner space opening downward. The upper wall and the pair of side walls include: a narrow portion and a wide portion wider in a right and left direction. The white key has right and left portions with respect to a center line of the narrow portion. The right and left portions are different in construction to adjust a balance of load between the right and left portions with respect to the center line.
US09508323B2
An image display method including: obtaining (S2301) combined data including (i) image data of an image having an item as a subject and (ii) first setting information indicating processing which a first electric appliance performs on the item; determining whether or not the first setting information is convertible into second setting information, the first setting information being included in the obtained combined data, and the second setting information being information in a format previously designated by a user and executable by a second electric appliance; determining (S2305) a first mark to be added to the image of the image data, if it is determined that the first setting information is convertible into the second setting information; and displaying (S2307) the image of the image data to which the determined first mark is added, the image data being included in the combined data.
US09508320B2
The present invention relates to a method for moving objects within the graphical user interface (GUI) of an operating system in a manner that provides a transitional effect between window states, which is pleasing to the user. This transitional effect includes changing the shape of a window while scaling and moving the window between two different sizes and positions. In one embodiment of the present invention, the transitional effect may be employed as a window is minimized into an icon, or restored from an icon. In another embodiment of the present invention, the transitional effect is employed as a window is minimized within its title bar, or restored therefrom. The rate of movement of objects is controlled in a non-linear manner, to further enhance the pleasing effect.
US09508307B2
An apparatus and method for automatically controlling screens displayed on two display units installed in a mobile terminal are provided, in which, an event is identified, if an event occurs, and on and off states of the display units are controlled, if the event is identified as a control operation of the display units corresponding to a user's key input. If the event is identified as a control operation of the display units corresponding to an operation of a sensor, the display units are automatically controlled corresponding to rotation of the mobile terminal.
US09508306B2
Disclosed is a display device comprising a panel in which a pixel is formed in each of a plurality of intersection areas between a plurality of data lines and a plurality of gate lines. Two or more data driver integrated circuits (ICs) supply data voltages to the plurality of data lines and a gate driver outputs a scan signal to the plurality of gate lines. A timing controller drives the data driver ICs and the gate driver. A plurality of gamma voltage generators generate gamma voltages respectively provided in the data driver ICs such that each of the data driver ICs generates data voltages using gamma voltages generated by another data driver IC of the two or more data driver ICs.
US09508305B2
A display device is provided that effectively reduces noise generated inside a display panel such as a liquid crystal panel. The source driving unit of the display device includes positive amplifiers, negative amplifiers, a positive amplifier regulating unit and a negative amplifier regulating unit. The positive amplifiers transmit positive driving signals to the display panel unit via source lines. The negative amplifiers transmit negative driving signals to the display panel via source lines. The positive amplifier regulating unit regulates the timing for the positive amplifiers to output positive driving signals. The negative amplifier regulating unit regulates the timing for the negative amplifiers to output negative driving signals.
US09508302B2
Exemplary embodiments of the present invention relate to a power supply of a display device that includes a driving circuit and a display panel that displays an image according to an output data voltage transmitted from the driving circuit. The power supply includes a first booster and a second booster provided in the driving circuit, the first booster generates a first output voltage supplied to an Op-amp of a source output circuit of the driving circuit, and the second booster generates a second output voltage supplied to buffers of the source output circuit of the driving circuit.
US09508300B2
A driving circuit includes: an input terminal; an output terminal; a first transistor having a source electrode coupled to the input terminal, a drain electrode coupled to the output terminal, and a gate electrode; a second transistor having a source electrode, a drain electrode, and a gate electrode respectively coupled to the source electrode, the drain electrode, and the gate electrode of the first transistor; a first capacitor having a first electrode coupled to the input terminal and a second electrode coupled to the output terminal; and a second capacitor coupled in parallel with the first capacitor and having a first electrode coupled to the first electrode of the first capacitor and a second electrode that is floated.
US09508276B2
In a second memory device, (n+1)th frame image data in an mth row (m is a natural number) is stored. In a comparator circuit, the nth frame image data in the mth row and the (n+1)th frame image data in the mth row are compared and determination data is output to a writing control circuit. In the writing control circuit, writing using the (n+1)th frame image data to a pixel in the mth row is not performed when the determination data indicates sameness, or the writing using the (n+1)th frame image data to the pixel in the mth row is performed when the determination data indicates difference. When performed in two or more successive frame periods, the writing using the (n+1)th frame image data is performed while video voltages having the same polarity are applied.
US09508273B2
A value oriented outdoor illuminated sign that is easily customizable is disclosed. It provides low energy use, efficient illumination for a minimum of 30 days when operated on included timer with no need for an extension cord or outlet.
US09508266B2
Anonymous pretesting items for subsequent presentation to participants in a group enable an instructor to validate responses and revise the items accordingly.
US09508265B2
According to one aspect, a flight controller constructed to control a parafoil in flight from a starting location to a target location is provided. The flight controller includes an interface constructed to connect to one or more actuators and one or more wind sensors, a memory, a processor coupled to the memory, the interface, and a flight manager component executable by the processor. The flight manager component is configured to identify the target location and the starting location, receive wind data, determine a relationship between a ground reference frame (GRF) and a wind fixed frame (WFF) based on the wind data, generate a trajectory between the starting location and the target location in the WFF, determine a desired heading based on the trajectory and the relationship between the GRF and the WFF, and generate an actuator control signal based on the desired heading to adjust a heading of the parafoil.
US09508261B2
A method for operating a vehicle, including the tasks of detecting a dynamic parameter of a preceding other vehicle, computing an assessment criterion based on the detected dynamic parameter, computing a setpoint vehicle trajectory as a function of the assessment criterion, and adjusting an actual vehicle trajectory to the setpoint vehicle trajectory. Also described is a corresponding device and a computer program.
US09508259B2
Provided is a wearable device including: a biological-signal sensing unit that senses a biological signal of a user; a vehicle-state sensing unit that senses a state where a vehicle that the user gets in is moved; and a controller that determines a parking mode and a parking direction using a result of the sensing by the vehicle-state sensing unit, when the vehicle is parked, and that measures a level of user tension for the parking mode and the parking direction that are determined using the biological signal that is sensed while the vehicle is being parked, in which the controller selects the parking mode and the parking direction that the user prefers, based on the measured level of user tension, and provides the user with information relating to a parking lot where the vehicle is able to be parked in the parking mode and the parking direction that are selected.
US09508256B2
Example apparatus and methods concern determining whether a target material appears in a region experiencing nuclear magnetic resonance. One method acquires a baseline value for a magnetic resonance parameter (MRP) while the region is not exposed to a molecular imaging agent that affects the MRP, acquiring a non-specific uptake value for the MRP while the sample is influenced by a non-specific molecular imaging agent and acquiring a specific uptake value for the MRP while the sample is influenced by a specific molecular imaging agent. The non-specific masking problem is solved by characterizing the region as a function of the baseline value, the non-specific uptake value, and the specific uptake value. The function relies on the similarities and differences between non-specific uptake of the non-specific molecular imaging agent, non-specific uptake of the specific molecular imaging agent, and specific uptake of the specific molecular imaging agent.
US09508251B1
Controls, devices, systems, and methods for remotely reversing ceiling fan rotation directions based on seasonal appearing indicia controls, and remotely selecting ceiling fan turn off times when the user falls asleep. Cooler weather indicia for a remote control reverse switch can include snowflake symbol and/or the types of seasonal weather indicators such as for winter time use. Warmer weather indicia for a remote control reverse switch can include a sun symbol and/or other types of seasonal weather conditions, such as for summer time. Sleep timer controls, such as buttons for 2 hours, 4 hours and 8 hours, allows the user to preset when the fan is to be turned off after the user decides to go to sleep.
US09508246B2
During charging of a mobile device by a charging coil, a charge controller acquires information of the seating position of the owner of the mobile device, through a short-range wireless communicating section, and therefore issues an alarm when a person who causes the mobile device to be charged performs an operation of leaving from the seating position. Consequently, it is possible to prevent the mobile device from being left in a vehicle.
US09508238B2
A system and device for detecting and/or deactivating a security tag when passing through an electronic article surveillance (EAS) portal. The portal may be oriented by the arrangement of one or more antennas to generate an electromagnetic field at or within the portal to detect and/or deactivate the security tag. The electromagnetic field may detect and/or deactivate a security tag located at any orientation on merchandise as the security tag passes through the portal. The portal may be mounted on a counter at a point-of-sale station in which merchandise having security tags attached thereto are passed through the portal. The portal may also be mounted to a floor in which a shopping cart having merchandise is passed through the portal so that security tags attached to the merchandise in the cart are detected and/or deactivated.
US09508236B2
A system that transforms a haptic signal receives the haptic signal, where the haptic signal includes a plurality of haptic effect patterns. The system detects one or more of the haptic effect patterns as a texture haptic effect pattern, where the detecting includes identifying a first haptic effect pattern having a texture duration value that is less than or equal to a pre-defined texture threshold value, and having a separation from a subsequent haptic effect pattern that is less than or equal to the pre-defined texture threshold value. The system then substitutes each detected texture haptic effect pattern within the haptic signal with one or more substitute texture haptic effect patterns to form a transformed haptic signal.
US09508225B2
Methods and systems for electronic interaction comprising a display for presenting a grid of identifying objects, an input for receiving a player selection of an identifying object, a random generator for randomly selecting a winning identifying object, and a point tally system for awarding points to the player according to the rules comprising a first point value if the player selected identifying object exactly matches the winning identifying object, a second point value if the player selected identifying object is in a geometric relationship with the winning identifying object, and a third, negative, point value if the player is not awarded the first point value or the second point value.
US09508219B2
A wagering game system and its operations are described herein. In some embodiments, the operations can include initiating, at a wagering game server, a secondary game for presentation on a wagering game machine. The secondary game may be associated with a primary wagering game being presented on the wagering game machine. The operations can also include detecting that the secondary game becomes unavailable for play while the secondary game is being presented on the wagering game machine, and determining identification information associated with a player of the primary wagering game and the secondary game. The operations can further include generating results for the secondary game associated with the player after the secondary game is available for play, and providing an award, depending on the secondary game results, to the player using the identification information.
US09508215B2
Systems and methods are provided for permitting a player to play a game at a gaming device. The gaming device provides a payout for the game. The payout is redeemable for one of a plurality of values, and at least two of the plurality of values are different from each other. The values typically have different corresponding forms of payout, such as cash or merchandise credits.
US09508182B2
A display apparatus includes a display panel and an active parallax barrier panel. The display panel displays n numbers of viewpoint images on a display panel (‘n’ is natural numbers greater than 2). The active parallax barrier panel includes a plurality of barrier units. Each of the barrier units includes an opening portion and a blocking area divided into m numbers of sub-areas. The active parallax barrier panel selectively opens the m numbers of sub-areas to exit the m numbers of viewpoint images on (n×m) numbers of viewpoint positions (‘m’ is natural numbers greater than 2). Thus, an active parallax barrier panel is time-division driven to display multi-viewpoint images. Moreover, a pixel structure and a barrier structure are alerted, so that deterioration of a resolution of a 3D image may be minimized.
US09508171B2
Disclosed is a method of rendering at least one graphical object comprising a plurality of sub parts described with a page description language format, said method comprising the steps of: converting the at least one graphical object into a first edge pair and a second edge pair, wherein the first edge pair and the second edge pair are vertically separated by a scanline gap; joining the second edge pair and the first edge pair to make a corresponding new edge pair having an empty fill portion in the scanline gap; and processing the new edge pair to render the at least one graphical object.
US09508168B2
A method and system render rasterized data by receiving non-rasterized page description language data and a corresponding transformation matrix representing transformation operations to be performed. The non-rasterized page description language data is rasterizing to create rasterized data. The corresponding transformation matrix is decomposed into a plurality of individual transformation operation matrices and a discrete transformation operation value, from each corresponding individual transformation operation matrix, is generated for each transformation operation to be performed upon the rasterized data. The transformation operations are performed upon the rasterized data based upon the generated discrete transformation operation values.
US09508165B1
A radiation detection system includes a detector unit and at least one processor. The detector unit is configured to generate signals responsive to radiation events. The at least one processor receives the signals, and is configured to obtain a first count for at least one of the signals corresponding to a first energy window, the first energy window corresponding to values higher than a nominal peak value; obtain a second count for the at least one of the signals corresponding to a second energy window, the second energy window corresponding to values lower than the nominal peak value; obtain at least one auxiliary count for the at least one of the signals corresponding to at least one auxiliary energy window; and adjust a gain applied to the signals based on the first count, the second count, and the at least one auxiliary count.
US09508163B2
A framework for an iterative reconstruction algorithm is described which combines two or more of an ordered subset method, a preconditioner method, and a nested loop method. In one type of implementation a nested loop (NL) structure is employed where the inner loop sub-problems are solved using ordered subset (OS) methods. The inner loop may be solved using OS and a preconditioner method. In other implementations, the inner loop problems are created by augmented Lagrangian methods and then solved using OS method.
US09508158B2
Automatic generation of custom palettes based on an image selected by a user is disclosed. In various embodiments, automatic palette generation may involve generating one or more than one palette based on the color or shading content of the image provided by the user. The generated palette may include a variety of colors (or shadings) that can be automatically mapped to and applied to various distinct features within a composite graphic construct to be customized.
US09508157B2
A framework for image-based reconstruction is provided herein. In accordance with one aspect, the framework receives three-dimensional projection image data of an aneurysm wall in a vascular structure of interest and electrocardiogram signal data, wherein the three-dimensional projection image data is correlated to phases of the electrocardiogram signal data. The framework may sort the three-dimensional projection image data into phase-binned image data according to the phases, and reconstruct three-dimensional layouts of the aneurysm wall in the vascular structure of interest using the phased-binned image data. The framework may then determine the motion of the aneurysm wall between the phases based on the reconstructed three-dimensional layouts.
US09508150B1
A non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to execute the stages of: calculating first curvature attributes of first areas of a first representation of a first three dimensional object; calculating second curvature attributes of second areas of a second representation of a second three dimensional object; selecting first points of interest of the first representation in response to the first curvature attributes; selecting second points of interest of the second representation in response to the second curvature attributes; classifying the first points of interest to first classes; classifying the second points of interest to second classes; calculating multiple sets of first vectors that are indicative of spatial relationships between first points of interest, wherein different sets out of the multiple sets of the first vectors are associated with different first classes; calculating multiple sets of second vectors that are indicative of spatial relationships between second points of interest, wherein different sets out of the multiple sets of the second vectors are associated with different second classes; and determining a misalignment between the first and second representations of the first and second objects in response to relationships between the multiple sets of first vectors and the multiple sets of the second vectors.
US09508148B2
A vision-guided alignment system to align a plurality of components includes a robotic gripper configured to move one component relative to another component and a camera coupled to a processor that generates an image of the components. A simulated robotic work cell generated by the processor calculates initial calibration positions that define the movement of the robotic gripper such that position errors between the actual position of the robotic gripper and the calibration positions are compensated by a camera space manipulation based control algorithm executed by the processor to control the robotic gripper to move one component into alignment with another component based on the image of the components.
US09508143B2
An apparatus and method thereof include an observation map generator configured to generate a three-dimensional (3D) observation map based on display frequency and/or display duration of a cross-sectional image of a 3D volume image, wherein the 3D observation map three-dimensionally represents degrees of interest for each voxel of the 3D volume image. The apparatus also includes a region of interest marker configured to mark a region of interest.
US09508135B1
An improved image processing system for enhancing a blurred image is described herein. According to an embodiment, a method for enhancing a blurred image provided by an image capturing device includes generating a standard gray low-resolution image by convoluting the blurred image with a Gaussian low-pass filter, extracting one or more high-frequency components from the standard gray low-resolution image, obtaining one or more higher-frequency nonlinear components by approximating the one or more high-frequency components, and adding the higher-frequency components to the blurred image.
US09508134B2
Described herein is a method for enhancing image data that includes transforming image data from an intensity domain to a wavelet domain to produce wavelet coefficients. A first set of wavelet coefficients of the wavelet coefficients includes low-frequency wavelet coefficients. The method also includes modifying the first set of wavelet coefficients using a coefficient distribution based filter to produce a modified first set of wavelet coefficients. The method includes transforming the modified first set of wavelet coefficients from the wavelet domain to the intensity domain to produce enhanced image data.
US09508131B2
Removal of the effects of dust or other impurities on image data is described. In one example, a model of artifact formation from sensor dust is determined. From the model of artifact formation, contextual information in the image and a color consistency constraint may be applied on the dust to remove the dust artifacts. Artifacts may also be removed from multiple images from the same or different cameras or camera settings.
US09508122B2
The present invention concerns a method, a system, a device for enrolling biometric data of a body part to be used for user authentication, using a two-dimensional sensor. The method comprises capturing, using the two-dimensional sensor, images representing different views of the body part, stitching the images into at least one mosaic, generating at least one constructed image by determining at least one area of interest in the mosaic, the area of interest representing an additional view of the body part, and extracting image data of the area of interest, and enrolling the constructed images in a set of templates to be used for user authentication.
US09508119B2
An electronic device and method of operation, the electronic device including at least one processor communicatively coupled to a display and memory, the processor configured for filtering a facial image rendered on the display. In an illustrative embodiment, the at least one processor is configured to generate a boundary around the facial image, the boundary having 2-dimensional x and y coordinates relative to boundaries of the display; store the coordinates in memory; in response to at least one of a cropping and moving of the image, recalculate the coordinates to match a new transform setting; and apply an effect to the facial image based on the updated coordinates.
US09508117B1
It is often desirable to register a first image to a second image, such as to form a panoramic image. The image registration technique discussed herein forms first and second gradients of the first and second images, respectively, then aligns phase vectors of the first and second gradients by estimating the parameters of a projective (homographic) coordinate transformation that can map the first gradient to the second gradient. The estimated parameters can be used to map the first image to the second image. In some examples, each gradient pixel includes a complex number, such as a unit vector, having a normalized amplitude and a phase vector that indicates the direction of greatest change, at that pixel, for the respective image. Aligning the image gradient phase vectors, rather than image intensity values, can align images produced under different lighting conditions, and/or produced in different wavelength regions of the electromagnetic spectrum.
US09508113B2
A pipeline system includes input buffers, a relay for controlling withdrawal of data stored in the input buffers, and functional blocks for performing one or more processing operations. A method of operating a pipeline system includes withdrawing data from one of input buffers and performing different one or more processing operations.
US09508108B1
Some embodiments provide a system that renders a user interface (UI) element for a web application. During operation, the system loads the web application in a web browser and obtains a rendering request for the UI element from the web application. Next, the system generates a graphics-processing unit (GPU) command stream corresponding to the UI element based on the rendering request. Finally, the system sends the GPU command stream to a GPU, where the UI element is rendered by the GPU.
US09508101B1
A system generates a ticker result, which may be a uniform resource locator (URL) corresponding to a quote provider. The system receives a string of information and determines whether all terms in the string of information correspond to ticker symbols. If all terms in the string of information correspond to ticker symbols, the system may ascertain whether the string of information corresponds to a query for ticker information. If the string of information corresponds to a query for ticker information, the ticker information (e.g., a ticker result) may be provided.
US09508088B2
An advertisement delivery management apparatus according to an embodiment includes an acquisition unit, a determination unit, and an accepting unit. The acquisition unit acquires information on two or more types of delivery target user groups, each including a plurality of delivery target users predicted as future advertisement delivery destinations. The determination unit determines whether each of the delivery target user groups satisfies delivery conditions designated by an advertisement delivery order request. The accepting unit accepts the advertisement delivery order request based on the determination result of the determination unit.
US09508086B2
Methods and apparatus to monitor, verify, and rate the performance of airings of commercials are disclosed. An example method includes analyzing received advertisement detection information associated with the advertisement, the advertisement detection information detected from a presentation of the advertisement; identifying a buy order corresponding to the presentation of the advertisement based on the advertisement detection information; determining a purchased ratings value from the buy order; comparing the purchased ratings value of the buy order to received ratings information corresponding to the presentation of the advertisement to determine whether the advertisement was presented as indicated in the buy order; and generating a performance monitoring report using the buy order and the advertisement detection information to indicate whether the ratings information is less than the purchased ratings value.
US09508078B1
Techniques for increasing the efficacy of an affiliate marketing program are described herein. These techniques may allow participants of the affiliate marketing program to easily create links to content that a content site offers. To do so, the content site may determine whether a user that requests content from the site is a participant of the program or a non-participant. Based at least in part on determining that the requesting user is a participant, the content site may serve the requested content in addition to a mechanism for creating links to the content. Furthermore, the mechanism may also illustrate or otherwise include content that is customized based on the content that the participant requests and/or based on an identity of the participant.
US09508075B2
A system that investigates, identifies and cancels fraudulent transactions comprises a fraud detection server that receives a first dataset indicating a quantity of fraud-transactions. The first dataset is generated at least in part by a fraud-score model. The system receives a second dataset including a quantity of false positive fraud-transactions from the fraud transactions. The system calculates a fraud error rate using the quantity of fraud-transactions and the quantity of false positive fraud-transactions. The system generates a new fraud-score model when the fraud error rate exceeds a predefined error rate.
US09508069B2
Methods and arrangements for effecting payments via a mobile phone. A purchase request is received from a merchant on behalf of a customer. A code is provided to the customer via the merchant, via a first communication path. A purchase confirmation is directly received from the customer, the purchase confirmation being prompted by provision of the code to the customer. The purchase is validated via using the purchase confirmation from the customer via a second communication path different from the first communication path. Other variants and embodiments are broadly contemplated herein.
US09508057B2
A method of one embodiment facilitates the updating of account information. First account information associated with a payment account of a user is received by an interface, and the first account information is stored by a memory. Payee system information associated with a payee system, wherein the payee system stores one or more portions of the first account information, is also received by the interface and stored by the memory. A processor automatically determines that an update event has occurred, the update event associated with updated information comprising one or more updated values for one or more respective portions of the first account information, wherein at least a portion of the first account information stored on the payee system changes based on the update event. In response to automatically determining that the update event has occurred, the interface automatically communicates a payee update message comprising the updated account information.
US09508055B1
A secure administration server sends legal hold information to a confirmation server in response to a delivery request. The legal hold information comprises a plurality of recipients required to comply with a legal hold notice. The secure administration server generates a unique email for each of the plurality of recipients. Each unique email comprises a unique Uniform Resource Locator (URL) to the confirmation server for a corresponding recipient. The secure administration server obtains a confirmation of compliance associated with the corresponding recipient from the confirmation server.
US09508045B2
The apparatus, systems, and methods described herein may operate to receive information identifying and describing at least one of a set of events, an initial distribution of a plurality of states, an initial transition matrix, or an initial event matrix; generate, based at least in part on the information, at least one intermediate transition matrix and at least one intermediate event matrix describing a sparse Baum-Welch training that allows no event to occur at one or more time steps; and transform the at least one intermediate transition matrix and the at least one intermediate event matrix into a transition matrix and an event matrix describing a continuous-time Baum-Welch training, the continuous-time Baum-Welch training allowing events to occur simultaneously or at sporadic time intervals in a Markov model including a hidden Markov Model (HMM) having more than two hidden states.
US09508041B2
The disclosure discloses a method for predicting a user operation. The method includes the following steps. After training an operation model successfully, a mobile terminal predicts a call instruction by utilizing environmental factors and the operation model, and finally compiles the call instruction into selection information to be displayed to a user. The disclosure further discloses a mobile terminal. Through the solution provided by the disclosure, a forthcoming operation of the user can be predicted, so that intelligent and detailed services are provided for the user.
US09508038B2
A computer-implemented system, method and program product generates answers to questions in an input query text string. The method includes determining, by a programmed processor unit, a lexical answer type (LAT) string associated with an input query; automatically obtaining a candidate answer string to the input query from a data corpus; mapping the query LAT string to a first type string in a structured resource; mapping the candidate answer string to a second type string in the structured resource; and determining if the first type string and the second type string are disjointed; and scoring the candidate answer string based on the determination of the types being disjointed wherein the structured resource includes a semantic database providing ontological content.
US09508037B2
A non-contact IC label of the present invention includes an IC chip disposed on a magnetic sheet, a first antenna section and a second antenna section each connected to the IC chip, a circuit section which connects a first end portion of the first antenna section and a first end portion of the second antenna section to the IC chip, a first auxiliary antenna section which is disposed to project from a side on the second end portion of the first antenna section and a second auxiliary antenna section which is disposed to project from a side on the second end portion of the second antenna section, wherein the first antenna section and the second antenna section are formed in the same rectangular shape in a plan view.
US09508036B2
An RFID tag assembly and method of use with a helmet wherein the RFID tag assembly the RFTD tag assembly includes an RFID tag having a mounting substrate with an exposed first planar surface and an opposing second planar surface, the RFID tag having an RFID semiconductor chip has a predetermined operating frequency with an antenna interface mounted on the second planar surface, a conductor electrically coupled to the antenna interface of the RFID semiconductor chip, and an antenna electrically coupled to the conductor. A spacer has a first surface and an opposing second surface. The first surface of the spacer is attached to the second planar surface of the RFID tag. The spacer has a predetermined thickness between the first surface and the second surface. A mounting carrier has a substantially planar body with a first portion having a first end and a second end with two sides defined therebetween and has one or more second portions extending from the body forming free ends each with a planar top surface and a planar bottom surface, with selectively attachable adhesive on a portion of the bottom surface being deformably attached to the first portion. The second surface of the spacer is attached to the top surface of the first portion with the first planar surface of the RFID tag position parallel and set apart above the top surface of the carrier by a distance equal to or greater than the predetermined thickness of the spacer.
US09508034B2
A system and method for the rapid bulk commissioning of RFID tags includes exploiting simultaneous writing of plural tags via isolated communications bands, avoiding write acknowledgement, collision/retransmission, and other delays.
US09508027B2
Systems, devices and methods operative for identifying a reference within a figure and an identifier in a text associated with the figure, the reference referring to an element depicted in the figure, the reference corresponding to the identifier, the identifier identifying the element in the text, placing the identifier on the figure at a distance from the reference, the identifier visually associated with the reference upon the placing, the placing of the identifier on the figure is irrespective of the distance between the identifier and the reference.
US09508022B2
A method and a device are provided for performing a recognition process. The recognition process compares an individual fingerprint view to a fingerprint enrollment template in order to determine whether a match has been found. The determination of a match is based on individual match statistics collected between the individual fingerprint view and each view of the fingerprint enrollment template. Additionally, inter-view match statistics between each view of the fingerprint enrollment template may also be determined. The inter-view match statistics can be analyzed along with the individual match statistics to further inform the determination of a match between the individual fingerprint view and the fingerprint enrollment template.
US09508017B2
Disclosed are a device for capturing an image of the iris and a user recognition device applying same in order to control access. According to one embodiment of the present invention, the device for capturing an image of the iris includes: a first light source corresponding to the left eye; a second light source corresponding to the right eye; a first duct disposed adjacent to the first light source for restricting the illumination angle of the first light source; a second duct disposed adjacent to the second light source for restricting the illumination angle of the second light source; a half mirror transmitting the light emitted from the first and second light sources in order to direct the light onto the left and right eyes, wherein the half mirror reflects the images of the left and right eyes; and left/right cameras respectively photographing the left and right eyes in order to recognize the irises.
US09508015B2
In a method for evaluating image data of a vehicle camera, information about raindrops on the vehicle's windshield within the field of view of the camera is taken into account in the evaluation of the image data for detection and classification of objects in the environment of the vehicle. Particularly, for example, depending on the number and the size of the raindrops on the windshield, different detection algorithms, image evaluation criteria, classification parameters, or classification algorithms are used for the detection and classification of objects.
US09508011B2
A video visual and audio query system for quickly identifying video within a large known corpus of videos being played on any screen or display. In one embodiment, the system can record via a mobile phone camera and microphone a live video clip from the TV and transcode it into a sequence of frame-signatures. The signatures representative of the clips can then be matched against the signatures of the TV content in a corpus across a network to identify the correct TV show or movie.
US09508002B2
A visualization system and method allow moving objects to be visualized in a GIS system as an interactive animation by moving an icon or 3D graphical model in an interactive virtual environment of the GIS. A line may also be drawn behind the icon/3D model representing the path traveled during a window of time. Additionally, the evolution of time-dependent data associated with the moving object may be encoded and visualized in the GIS.
US09507997B2
Implementations and techniques for measuring quality of experience associated with a mobile device are generally disclosed.
US09507990B2
The embodiments of the disclosure provide a two-dimensional code recognition method and associated apparatus. The two-dimensional code recognition method comprises steps of determining whether there is a picture displayed on a screen; determining whether the picture includes a two-dimensional code, when the picture is displayed on the screen; and identifying the two-dimensional code, when the picture includes the two-dimensional code. According to the disclosure only when determining the picture includes a two-dimensional code, the two-dimensional code is identified, and cameras are not required for the recognition of the local two-dimensional code picture.
US09507984B1
Embodiments of the invention are directed to a system, method, or computer program product for generating resource tag systems and integration of the tag systems on machines for machine use, valuation, and distribution. The tags comprise sensors for monitoring activity of the machine or product and identifies stagnant periods in the use of the machine or product. Based on a triggering stagnant duration, the tag system provides signals to the user indicating product inactivity. The tag may generate a communicable link with outside sources to identify and present the user with a current market value of the machine or product that the tag is affixed. Upon authorization, the tag may post the machine or product for sale and/or present the product for donation. Furthermore, upon sale of the product, the tag may be able to transfer warranty information along with the product.
US09507966B2
According to one embodiment, a firmware stored in a ROM in an information processing device connects the information processing device to a first server through a network, and downloads a client program into a volatile memory in the information processing device from the first server. Also, the firmware launches the client program to connect the information processing device and a second server through the network, and turns off the power of the information processing device to erase content in the volatile memory, when the information processing device is disconnected from the network after connection between the information processing device and the second server is established.
US09507964B2
Described herein are techniques for regulating access to a remote resource using two-factor authentication based on information regarding a host machine of a portable storage drive that stores an operating system that is booted by the host machine. The information regarding the host machine of a portable storage drive may be used as a second factor in a two-factor authentication. Such information regarding the host machine may include, in some embodiments, information retrieved from a secure storage of the host machine, such as from a cryptoprocessor of the host machine. The information may include an identifier for the host machine or may be a user credential pre-provisioned to the host machine to be used in two-factor authentication.
US09507963B2
A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.
US09507961B2
Systems, methods, and computer programs are disclosed for providing secure access control to a graphics processing unit (GPU). One system includes a GPU, a plurality GPU programming interfaces, and a command processor. Each GPU programming interface is dynamically assigned to a different one of a plurality of security zones. Each GPU programming interface is configured to receive work orders issued by one or more applications associated with the corresponding security zone. The work orders comprise instructions to be executed by the GPU. The command processor is in communication with the plurality of GPU programming interfaces. The command processor is configured to control execution of the work orders received by the plurality of GPU programming interfaces using separate secure memory regions. Each secure memory region is allocated to one of the plurality of security zones.
US09507955B2
The various embodiments of the invention provide a method for executing code securely in a general purpose computer. According to one embodiment, a code is downloaded into a cache memory of a computer in which the code is to be executed. The code downloaded into the cache memory is encrypted in the cache memory. Then the encrypted code in the cache memory is decrypted using a decryption algorithm to obtain the decrypted code. The decrypted code is executed in the cache to generate a result. The decrypted code is destroyed in the cache memory after the forwarding the result to a user.
US09507935B2
An exploit detection system deploys a threat-aware microvisor to facilitate real-time security analysis, including exploit detection and threat intelligence, of an operating system process executing on a node of a network environment. The microvisor may be organized as a main protection domain representative of the operating system process. In response to the process attempting to access a kernel resource for which it does not have permission, a capability violation may be generated at the main protection domain of the microvisor and a micro-virtual machine (VM) may be spawned as a container configured to encapsulate the process. The main protection domain may then be cloned to create a cloned protection domain that is representative of the process and that is bound to the spawned micro-VM. Capabilities of the cloned protection domain may be configured to be more restricted than the capabilities of the main protection domain with respect to access to the kernel resource. The restricted capabilities may be configured to generate more capability violations than those generated by the capabilities of the main protection domain and, in turn, enable further monitoring of the process as it attempts to access the kernel resource.
US09507925B2
A mobile communications device includes a plurality of first input devices capable of passively collecting input data, a second input device(s) capable of collecting response data based upon a challenge, and a processor capable of determining a level of assurance (LOA) that possession of the mobile communications device has not changed based upon a statistical behavioral model and the passively received input data, and comparing the LOA with a security threshold. When the LOA is above the security threshold, the processor may be capable of performing a given mobile device operation without requiring response data from the second input device(s). When the LOA falls below the security threshold, the processor may be capable of generating the challenge, performing the given mobile device operation responsive to valid response data, and adding recent input data to the statistical behavioral model responsive to receipt of the valid response data.
US09507918B2
A platform protected by an always-available security system, the system is described. The system, in one embodiment, comprises a near field communications (NFC) reader, a pairing logic to identify an NFC device as an authorized device for arming and disarming the system, an arming logic to arm the system upon receipt of an arming command, and a disarming logic to disarm the system upon receipt of a disarming command, wherein the arming command and the disarming command may use the NFC device, and wherein the NFC reader is powered in a plurality of power states, enabling disarming and arming of the platform in the plurality of power states.
US09507911B2
A system and method are disclosed for one-stop shopping for health-care services and related needs. The one-stop shopping system and method provide objective information for the system enrollee to assess and decide on health-care insurance and services. The system and method provide this objective information in a way that is easily accessible by system enrollees in an economical and rapid manner.
US09507908B2
A method for creating a computerized visualization of a wiring topology is described that includes combining three-dimensional wire harness data with logical wire content using a process executed on a computer processing device, and displaying a graphical wire topology, output from the process, within a three dimensional model of the platform within which the wiring topology is contained.
US09507905B2
A non-transitory recording medium storing a program that causes a computer to execute a circuit board design assistance process. The circuit board design assistance process includes: extracting, from design information of a multilayer circuit board in which a plurality of layers are layered, a plurality of ground patterns in the multilayer circuit board that are within a predetermined distance from a path of a signal that flows in the multilayer circuit board; resolving a region at which the plurality of ground patterns are electronically separated as being a discontinuity region; and displaying the resolved discontinuity region.
US09507903B2
A method for the simulation of a circuit is disclosed. The method may include the determination of parasitic circuit elements, and the determination of one or more operational parameters dependent upon at least the parasitic circuit elements. A model of the parasitic circuit elements may then be generated based upon the one or more operational parameters. The circuit may then be simulated using the model of the parasitic circuit elements to determine a performance level of the circuit. At least one active circuit element may be modified in response to determining that the performance level does not meet a goal.
US09507900B2
Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.
US09507897B2
One or more circuit arrangements and techniques for modeling are provided. In some embodiments, a circuit arrangement includes at least one of a first current source, a second current source, a first diode, a second diode, and a switching component. In some embodiments, the switching component includes a bipolar junction transistor (BJT). In some embodiments, the circuit arrangement is integrated into a metal oxide semiconductor (MOS) device. When the circuit arrangement is integrated into a MOS device, at least one of a substrate current leakage, a junction breakdown, or a diode reverse recovery (DRR) effect is predictable for the MOS device.
US09507895B2
A simulation apparatus includes a discrete events simulation section to perform a discrete type simulation of components of a configured model as defined based on attribute information that is information on parts of the components of the defined configured model and connection information showing a connectional relationship among the components of the defined configured model; and a soft error rate computation processing section to compute a soft error rate of the defined configured model based on the simulation result of the discrete events simulation section and data on soft error rates in the attribute information.
US09507884B2
A modeling system and modeling method based on a logical relation, including an operation task integrating module, a task interpreter, a graph layout correcting module, a graph wiring correcting module and a database model increment correcting module, wherein the database model increment correcting module includes a graph increment calculating unit and a model increment calculating unit. The system, through description of the logical relation and based on support of the automatic wiring technology, realizes the graph-model integrated generation of a new grid model of the power system which is based on the description of the logical relation; the grid model is completely defined and modified on “one net”, which is different from the original way that the power system model is established on countless net graphs, thereby helping the grid operation manager to accurately and rapidly establish and modify the grid model of the full system.
US09507883B2
A method for designing a system on a target device includes mapping a high-level description of the system onto a model of a target device prior to generating a register transfer level description of the system. A visual representation of the mapping is generated.
US09507882B1
Described is a dynamic web platform configured to provide content rendered with one or more rendering systems. The rendering systems and the modules making up the rendering modules may interact with one another by way of declarative data. Administrators may configure the platform using the declarative data. The declarative data may express operational parameters, business rules, and so forth and may be modified while the platform is operating. The modules in the rendering system may be loosely bound, allowing for concurrent operations, dynamic changes to what content is to be rendered, and so forth.
US09507878B2
A search system generates customized search results for social network members. The results are responsive to queries and are personalized based on members' explicit and implicit interests derived from user actions, content selections, etc.
US09507874B2
Within a system comprising a processor and a memory, a method that includes, via the processor, receiving a schema as an input. For each element in the schema, the method can include parsing the element from the schema, validating the parsed element, generating a parse tree node for the parsed element, and adding the parse tree node to a schema parse tree. The method further can include outputting the schema parse tree.
US09507867B2
A method that is relatively inexpensive to implement and that permits a user to conduct searches of electronically stored documents using an entire document, multiple documents or portions of a document as the search criteria and to collect, store and to share the relevant documents from the search.
US09507854B2
A method, system and computer program product for generating answers to questions. In one embodiment, the method comprises receiving an input query; conducting a search to identify candidate answers to the input query, and producing a plurality of scores for each of the candidate answers. For each of the candidate answers, one, of a plurality of candidate ranking functions, is selected. This selected ranking function is applied to the each of the candidate answers to determine a ranking for the candidate answer based on the scores for that candidate answer. One or more of the candidate answers is selected, based on the rankings for the candidate answers, as one or more answers to the input query. In an embodiment, the ranking function selection is performed using information about the question. In an embodiment, the ranking function selection is performed using information about each answer.
US09507853B1
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obtaining one or more first search results that were generated for a search query; determining a score associated with the first search results; revising the search query using a query revision rule; obtaining one or more second search results that were generated for the revised search query; determining a score associated with the second search results; and evaluating the query revision rule by comparing the score associated with the first search results with the score associated with the second search results.
US09507846B2
A method for configuring a control interface for controlling a system including one or more pieces of home automation equipment, the control interface including an information screen on which may be displayed a time scale representing a time period with a defined duration, the method including steps of: (i): defining a plurality of associations, each association being defined between a scenario for controlling one or more pieces of home automation equipment and a triggering instant defined within the time period, at which the scenario has to be triggered by the control interface, (ii): producing a grouping of at least one portion of the association from among the plurality of defined associations, the triggering instants of which are defined within a time interval with a defined duration within the time period, (iii): positioning a collective reference mark on the time scale corresponding to the grouping at the time interval.
US09507845B1
A system, program product, and computer implemented method for replicating a consistency group comprising monitoring the latency between one or more splitters of the consistency group and replication appliances in the replication cluster for the consistency group (CG); wherein each replication appliance of the replication appliances is configured to be able to receive IO from the one or more splitters, determining which replication appliance of the replication appliances has the lowest latency after including additional latency resulting from assignment of the CG to the replication appliance, and configuring the splitter to replicate IO from the CG to the replication appliance determined to have the lowest latency.
US09507844B2
A processor determines a predicted quantity of updates to be made to a set of data using a history of updates. The set of data is associated with a category of replication that indicates a first frequency of data replication to be applied to the set of data. The processor determines whether the first predicted quantity of updates meets a first threshold for a frequency of replication of the set of data. The first threshold indicates an allowed number of updates and meeting the first threshold indicates that an adjustment to the frequency of replication of the set of data is to be initiated. The processor responds to a determination that the first threshold has been met by associating the set of data with a category of replication that has a second frequency of data replication to be applied to the set of data.
US09507823B2
A method and system for accessing data in a de-commissioned legacy system are provided. Data are automatically extracted from the legacy system, although data structure(s) of the legacy system might not be known, by finding views corresponding to a query for the data. Attributes, metadata, and/or fields (“attributes”) can be parsed from the query. Tables and/or fields including the parsed attributes are identified. Views can be then identified, where the views contain the tables and/or fields including the parsed attributes. The views can be ranked in an order from those that include the greatest number of parsed attributes to those including the least number of parsed attributes. A data request understandable by the legacy system, e.g. a packet, can then be formed using the least number of views, where the views can collectively include all of the parsed attributes.
US09507822B2
Methods and systems for optimizing queries in a multi-tenant store are described. In one embodiment, such a method includes retrieving data from a multi-tenant database system having a relational data store and a non-relational data store, receiving a request specifying data to be retrieved, retrieving one or more locations of the data to be retrieved, generating a database query based on the request, in which the database query specifies a plurality of data elements to be retrieved, the plurality of data elements including one or more data elements residing within the non-relational data store and one or more other data elements residing within the relational data store, generating an optimized database query having an optimized query syntax that is distinct from a query syntax of the database query, and executing the optimized database query against the multi-tenant database system to retrieve the data.
US09507821B2
Electronic mail message processing includes: obtaining a set of keywords associated with an electronic mail message; updating, based at least in part on the set of keywords, a set of inverted index records stored in a level 1 cache; determining whether size of the set of inverted index records stored in the level 1 cache exceeds a first preset threshold value; in the event that the first preset threshold value is exceeded, transferring the set of inverted index records in the level 1 cache to a level 2 cache; determining whether size of a level 2 cache file exceeds a second preset threshold value; in the event that the second preset threshold value is exceeded, transferring, according to a path file, inverted index records in the level 2 cache file to a level 3 cache storing a set of inverted index files.
US09507814B2
A bit level file comparison system compares two file systems, each of which includes any number of individual files, to determine whether the file systems are identical at a bit level. A hashing function is applied to each file in the first file system to generate a hash value that is logically associated with the respective file in the first file system. The hashing function is applied to each file in the second file system to generate a hash value that is logically associated with the respective file in the second file system. The hash value associated with a file in the first file system is compared with the hash value associated with the corresponding file in the second file system to determine whether bit level differences between the respective file in the first file system and the second file system.
US09507809B2
Systems, apparatuses, and methods can provide parameters of operating results for control products used in biological reactions. For example, automatically updated inserts containing such parameters for clinical quality controls can be provided. A customer can log into a website, provide lot number of quality control products, information about instruments, and tests being performed and then receive updated parameters for the products. The product inserts can be customized for or by a particular customer.
US09507808B2
A technique for structuring a navigation data base in order to support incremental data updates is provided. A method implementation of the technique includes the steps of providing at least two data levels, wherein a first data level is associated with route links representing road segments of regional distance roads, partitioning the first data level into local tiles, wherein each local tile is associated with route links representing road segments of regional distance roads for a specific local geographic area, and interlinking those route links of neighboring local tiles that represent road segment portions of a regional distance road extending over neighboring local tiles.
US09507806B1
A method of delivering images by an edge server to a web browser is disclosed. It includes receiving through an interface a request for an image file. It includes detecting by a processor the image file as a non-interlaced image file. It includes converting by the processor the detected non-interlaced image file to a corresponding interlaced image file. It includes sending a first segment of the corresponding interlaced image file in response to the request for the image file and delaying delivery of a second segment of the corresponding interlaced image file until a subsequent request for the second segment of the corresponding interlaced image file is received.
US09507803B2
Systems, methods, and computer-readable storage media for web-scale visual search capable of using a combination of visual input modalities are provided. An edgel index is created that includes shape-descriptors, including edgel-based representations, that correspond to each of a plurality of images. Each edgel-based representation includes pixels that depicts edges or boundary contours of an image and is created, at least in part, by segmenting the image into a plurality of image segments and performing a multi-phase contour detection on each segment. Upon receiving a search query having a visual query input, the visual query input is converted into shape-descriptors, including an edgel-based representation, and the shape-descriptors, including the edgel-based representation, of each of the plurality of images is compared with the shape-descriptors, including the edgel-based representation, of the visual query input to identify at least one image of the plurality of images that matches the visual query input.
US09507798B1
A technique for logging events in a data storage system involves designating one subset of storage processors of the data storage system as clients that generate log entries and another subset of the storage processors as servers that receive log entries. Only one server is active at a time. The active server receives the generated log entries from the clients and persists the log entries to a centralized log store. Clients assign first timestamps to the log entries based on locally accessible clocks. The active server receives the log entries, including the first timestamps, from the clients and applies second timestamps based on a clock accessible to the server. As the second timestamps are consistent across the different clients, the second timestamps can be applied to correct misalignments in time among the log entries received from the clients.
US09507797B2
A file system is to be shared by multiple file servers according to respective different file server protocols, and the file system is to implement cross-protocol locking in access of file system objects of the file system. A file system denies access to a particular file system object from a first file server protocol in response to a data structure referred to by an inode indicating that an access from a second different file server protocol of the particular file system object is present.
US09507766B2
In one embodiment, a computer-implemented method includes writing, into a tree content column of a tree table, content for a plurality of rows of the tree table. The content spans multiple hierarchical levels, and the content in each of the rows is commonly aligned within the tree content column. A level-indicating icon is associated with each of the hierarchical levels of the tree table. A first level-indicating icon for a first hierarchical level of the tree table is positioned in two or more distinct rows of the tree table having content in the first hierarchical level, and a second level-indicating icon for a second hierarchical level of the tree table is positioned in at least one row of the tree table having content in the second hierarchical level. The tree table is rendered by a computer processor.
US09507765B2
Approaches are described for displaying rotated character strings within cells of tables. In particular embodiments, the display of the rotated character string is handled such that the character string does not extend beyond the edges of the cell. Further, in certain implementations, the character string may be displayed as wrapped and rotated text within the cell, wherein each line of the wrapped character string does not extend beyond the edges of the cell.