Invention Grant
- Patent Title: Coarse delay lock estimation for digital DLL circuits
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Application No.: US16392184Application Date: 2019-04-23
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Publication No.: US11018676B2Publication Date: 2021-05-25
- Inventor: Fangxing Wei , Khushal Chandan , Dan Shi , Michael Allen
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: H03L7/08
- IPC: H03L7/08 ; H03L7/081 ; H03L7/091 ; G11C11/56 ; G11C7/14 ; H03L7/10
Abstract:
Digital delay locked loop circuits, devices systems, and associated methods are provided and described. Such devices, systems, and methods utilize an open loop measurement for establishing a coarse delay lock.
Public/Granted literature
- US20200007132A1 COARSE DELAY LOCK ESTIMATION FOR DIGITAL DLL CIRCUITS Public/Granted day:2020-01-02
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