Invention Grant
- Patent Title: Technologies for power tunnels on circuit boards
-
Application No.: US17212016Application Date: 2021-03-25
-
Publication No.: US12156331B2Publication Date: 2024-11-26
- Inventor: Khai Ern See , Jia Lin Liew , Tin Poay Chuah , Chee How Lim , Yi How Ooi
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: H05K1/02
- IPC: H05K1/02 ; H01L21/3105 ; H05K1/11 ; H05K3/00 ; H05K3/42

Abstract:
Techniques for power tunnels on circuit boards are disclosed. A power tunnel may be created in a circuit board by drilling through non-conductive layers to a conductive trace and then filling in the hole with a conductor. A power tunnel can have a high cross-sectional area and can carry a larger amount of current than an equivalent-width trace, reducing the area on a circuit board required to carry that amount of current.
Public/Granted literature
- US20210212205A1 TECHNOLOGIES FOR POWER TUNNELS ON CIRCUIT BOARDS Public/Granted day:2021-07-08
Information query