-
公开(公告)号:US20210120699A1
公开(公告)日:2021-04-22
申请号:US17132846
申请日:2020-12-23
Applicant: Intel Corporation
Inventor: Chee How Lim , Khai Ern See , Chin Kung Goh , Twan Sing Loo
Abstract: Fan module interconnect apparatus are disclosed. An example fan module includes a fan and a fan housing to carry the fan. The fan is to rotate in the fan housing. A flange extends from the fan housing and including signal paths to provide an interconnect to electrically couple at least portions of a first electrical circuit and a second electrical circuit of an electronic device.
-
公开(公告)号:US20210212205A1
公开(公告)日:2021-07-08
申请号:US17212016
申请日:2021-03-25
Applicant: Intel Corporation
Inventor: Khai Ern See , Jia Lin Liew , Tin Poay Chuah , Chee How Lim , Yi How Ooi
Abstract: Techniques for power tunnels on circuit boards are disclosed. A power tunnel may be created in a circuit board by drilling through non-conductive layers to a conductive trace and then filling in the hole with a conductor. A power tunnel can have a high cross-sectional area and can carry a larger amount of current than an equivalent-width trace, reducing the area on a circuit board required to carry that amount of current.
-
公开(公告)号:US12156331B2
公开(公告)日:2024-11-26
申请号:US17212016
申请日:2021-03-25
Applicant: Intel Corporation
Inventor: Khai Ern See , Jia Lin Liew , Tin Poay Chuah , Chee How Lim , Yi How Ooi
IPC: H05K1/02 , H01L21/3105 , H05K1/11 , H05K3/00 , H05K3/42
Abstract: Techniques for power tunnels on circuit boards are disclosed. A power tunnel may be created in a circuit board by drilling through non-conductive layers to a conductive trace and then filling in the hole with a conductor. A power tunnel can have a high cross-sectional area and can carry a larger amount of current than an equivalent-width trace, reducing the area on a circuit board required to carry that amount of current.
-
公开(公告)号:US11445608B2
公开(公告)日:2022-09-13
申请号:US16903845
申请日:2020-06-17
Applicant: Intel Corporation
Inventor: Chee How Lim , Eng Huat Goh , Jon Sern Lim , Khai Ern See , Min Suet Lim , Tin Poay Chuah , Yew San Lim
Abstract: An electronic device may include a chassis. The electronic device may include a first electronic component that may include a first substrate and a first interconnect. The electronic device may include a second electronic component that may include a second substrate and a second interconnect. The second substrate may be physically separated from the first substrate. An electrical trace may be coupled to the chassis of the electronic device. The electrical trace may be sized and shaped to interface with the first interconnect of the first electronic component. The electrical trace may be sized and shaped to interface with the second interconnect of the second electronic component. The first electronic component and the second electronic component may be in electrical communication through the electrical trace coupled to the chassis of the electronic device.
-
公开(公告)号:US20210100101A1
公开(公告)日:2021-04-01
申请号:US16903845
申请日:2020-06-17
Applicant: Intel Corporation
Inventor: Chee How Lim , Eng Huat Goh , Jon Sern Lim , Khai Ern See , Min Suet Lim , Tin Poay Chuah , Yew San Lim
Abstract: An electronic device may include a chassis. The electronic device may include a first electronic component that may include a first substrate and a first interconnect. The electronic device may include a second electronic component that may include a second substrate and a second interconnect. The second substrate may be physically separated from the first substrate. An electrical trace may be coupled to the chassis of the electronic device. The electrical trace may be sized and shaped to interface with the first interconnect of the first electronic component. The electrical trace may be sized and shaped to interface with the second interconnect of the second electronic component. The first electronic component and the second electronic component may be in electrical communication through the electrical trace coupled to the chassis of the electronic device.
-
-
-
-