Invention Grant
- Patent Title: Integration of ALD barrier layer and CVD Ru liner for void-free Cu filling
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Application No.: US14613086Application Date: 2015-02-03
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Publication No.: US09607888B2Publication Date: 2017-03-28
- Inventor: Kai-Hung Yu , Toshio Hasegawa , Tadahiro Ishizaka , Manabu Oie , Fumitaka Amano , Steven Consiglio , Cory Wajda , Kaoru Maekawa , Gert J. Leusink
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/285 ; H01L23/532 ; C23C16/04 ; C23C16/34
Abstract:
Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.
Public/Granted literature
- US20150221550A1 INTEGRATION OF ALD BARRIER LAYER AND CVD Ru LINER FOR VOID-FREE Cu FILLING Public/Granted day:2015-08-06
Information query
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