公开(公告)号：US20240363410A1

公开(公告)日：2024-10-31

申请号：US18620326

申请日：2024-03-28

Applicant: Tokyo Electron Limited

Inventor： Ryota Yonezawa ,  Kai-Hung Yu ,  Yuji Otsuki ,  Kenichi Imakita ,  Atsushi Gomi ,  Kohichi Satoh ,  Tadahiro Ishizaka ,  Takashi Sakuma ,  Hidenao Suzuki

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76804 ,  H01L21/76805

Abstract: A method for forming a semiconductor device can include providing a substrate including a via in a dielectric layer, forming a ruthenium metal plug in the via, and at least part of the ruthenium metal plug can be formed directly on the dielectric layer in the via, forming a metal cap layer directly on the ruthenium metal plug, and forming a metallization layer, such as a copper-containing trench, over the ruthenium metal plug, such that the metal cap layer is between the metallization layer and the ruthenium metal plug, which can prevent intermixing of the ruthenium of the ruthenium metal plug with the metal or metals in the metallization layer.

公开(公告)号：US20220301882A1

公开(公告)日：2022-09-22

申请号：US17835056

申请日：2022-06-08

Applicant: TOKYO ELECTRON LIMITED

Inventor： Koichi Takatsuki ,  Tadahiro Ishizaka ,  Mikio Suzuki ,  Toshio Hasegawa

IPC: H01L21/311 ,  H01L21/285 ,  C23C16/455 ,  C23C16/02 ,  C23C16/06 ,  H01L21/768

Abstract: There is provided a method of performing a surface processing on a substrate having a metal layer formed on a bottom portion of a recess formed in an insulating film, the method including: supplying a halogen-containing gas into a processing chamber in which the substrate is loaded; and removing a metal oxide from the bottom portion of the recess using the halogen-containing gas.

公开(公告)号：US20180254181A1

公开(公告)日：2018-09-06

申请号：US15899602

申请日：2018-02-20

Applicant: Tokyo Electron Limited

Inventor： Tadahiro Ishizaka

IPC: H01L21/02 ,  H01L21/321 ,  H01L21/324

CPC classification number: H01L21/0262 ,  C23C16/045 ,  C23C16/16 ,  C23C16/18 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/28556 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53266

Abstract: A first aspect of the present disclosure provides a ruthenium wiring manufacturing method of manufacturing a ruthenium wiring by filling a recess, with respect to a substrate including a predetermined film having the recess formed in a surface thereof. The method includes: embedding a first ruthenium film in the recess by forming the first ruthenium film by CVD using a ruthenium raw material gas; forming an additional layer by forming a second ruthenium film on the first ruthenium film embedded in the recess by CVD using the ruthenium raw material gas at a film forming rate higher than that at a time of embedding; and flattening the second ruthenium film and the first ruthenium film by removing the second ruthenium film and the first ruthenium film on the substrate surface by CMP.

公开(公告)号：US10056328B2

公开(公告)日：2018-08-21

申请号：US15651979

申请日：2017-07-17

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Gerrit J. Leusink ,  Cory Wajda ,  Tadahiro Ishizaka ,  Takahiro Hakamata

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/5226 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L23/53242

Abstract: A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature.

公开(公告)号：US09406557B2

公开(公告)日：2016-08-02

申请号：US14316251

申请日：2014-06-26

Applicant: TOKYO ELECTRON LIMITED

Inventor： Osamu Yokoyama ,  Cheonsoo Han ,  Takashi Sakuma ,  Chiaki Yasumuro ,  Tatsuo Hirasawa ,  Tadahiro Ishizaka ,  Kenji Suzuki

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/288

CPC classification number: H01L21/76877 ,  H01L21/2885 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76867 ,  H01L21/76876 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming a copper (Cu) wiring in a recess formed to have a predetermined pattern in an insulating film formed on a surface of a substrate. The method includes: forming a barrier film at least on a surface of the recess, the barrier film serving as a barrier for blocking diffusion of Cu; forming a Ru film on the barrier film by Chemical Mechanical Deposition (CVD); forming a Cu alloy film on the Ru film by Physical Vapor Deposition (PVD) to bury the recess; forming a Cu wiring using the Cu alloy film buried in the recess; and forming a dielectric film on the Cu wiring.

Abstract translation: 提供了在形成在基板表面上的绝缘膜中形成为具有预定图案的凹部中形成铜（Cu）布线的方法。 所述方法包括：至少在所述凹部的表面上形成阻挡膜，所述阻挡膜用作阻挡Cu的扩散的阻挡层; 通过化学机械沉积（CVD）在阻挡膜上形成Ru膜; 通过物理气相沉积（PVD）在Ru膜上形成Cu合金膜以埋藏凹槽; 使用埋在凹部中的Cu合金膜形成Cu布线; 并在Cu布线上形成电介质膜。

公开(公告)号：US09362166B2

公开(公告)日：2016-06-07

申请号：US14642331

申请日：2015-03-09

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tadahiro Ishizaka ,  Takashi Sakuma ,  Osamu Yokoyama ,  Kenji Matsumoto ,  Peng Chang ,  Hiroyuki Nagai

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76876 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a copper wiring buried in a recess portion of a predetermined pattern formed in an interlayer insulation layer of a substrate is disclosed. The method includes: forming a manganese oxide film at least on a surface of the recess portion, the manganese oxide film serving as a self-aligned barrier film through reaction with the interlayer insulation layer; performing hydrogen radical treatment with respect to a surface of the manganese oxide film; placing a metal more active than ruthenium on the surface of the manganese oxide film after the hydrogen radical treatment; forming a ruthenium film on the surface where the metal more active than ruthenium is present; and forming a copper film on the ruthenium film by physical vapor deposition (PVD) to bury the copper film in the recess portion.

Abstract translation: 公开了一种埋设在衬底的层间绝缘层中形成的预定图案的凹部中的铜布线的形成方法。 该方法包括：通过与层间绝缘层反应，至少在凹部的表面上形成氧化锰膜，氧化锰膜作为自对准阻挡膜; 相对于氧化锰膜的表面进行氢自由基处理; 在氧自由基处理之后，将比钌更金属的氧化物膜置于氧化锰膜的表面上; 在其上存在比钌更有活性的金属的表面上形成钌膜; 并通过物理气相沉积（PVD）在钌膜上形成铜膜以将铜膜埋入凹部中。

公开(公告)号：US20150221550A1

公开(公告)日：2015-08-06

申请号：US14613086

申请日：2015-02-03

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Toshio Hasegawa ,  Tadahiro Ishizaka ,  Manabu Oie ,  Fumitaka Amano ,  Steven Consiglio ,  Cory Wajda ,  Kaoru Maekawa ,  Gert J. Leusink

IPC: H01L21/768

CPC classification number: H01L21/76846 ,  C23C16/045 ,  C23C16/34 ,  H01L21/28562 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.

Abstract translation: 在几个实施例中公开了用于整合用于半导体器件的窄凹陷特征的Cu填充的Ru衬垫的阻挡层的原子层沉积（ALD）和化学气相沉积（CVD）的方法。 根据一个实施方案，该方法包括提供含有凹陷特征的基底，在凹陷特征中通过ALD沉积共形阻挡层，其中阻挡层包含TaN或TaAlN，通过CVD在阻挡层上沉积共形Ru衬垫;以及 用Cu金属填充凹陷特征。

公开(公告)号：US09101067B2

公开(公告)日：2015-08-04

申请号：US14136838

申请日：2013-12-20

Applicant: Tokyo Electron Limited

Inventor： Tadahiro Ishizaka ,  Toshio Hasegawa

IPC: H01B13/00 ,  H05K3/10 ,  H05K3/14 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K3/107 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2924/0002 ,  H05K3/146 ,  H05K3/388 ,  H05K3/465 ,  H05K2203/095 ,  H05K2203/1338 ,  H05K2203/1476 ,  H01L2924/00

Abstract: In a Cu wiring forming method for forming a Cu wiring by filling Cu in a recess which is formed in a substrate in a predetermined pattern, a barrier film formed of a TaAlN film is formed at least on the surface of the recess by thermal ALD or thermal CVD. Then a Cu film is formed to fill the recess with the Cu film. Further, the Cu wiring is formed in the recess by polishing the entire surface of the substrate by CMP.

Abstract translation: 在通过以预定图案填充在基板中的凹部中填充Cu的Cu布线形成方法中，通过热ALD或至少在凹部的表面上形成由TaAlN膜形成的阻挡膜， 热CVD。 然后形成Cu膜以用Cu膜填充凹部。 此外，通过CMP对衬底的整个表面进行抛光而在凹部中形成Cu布线。

公开(公告)号：US20240213093A1

公开(公告)日：2024-06-27

申请号：US18145582

申请日：2022-12-22

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Hiroak Niimi ,  Robert D. Clark ,  Tadahiro Ishizaka

IPC: H01L21/768

CPC classification number: H01L21/76879

Abstract: A method for processing a substrate that includes: treating the substrate with a halogen-containing catalyst, the substrate including a semiconductor layer, a dielectric layer disposed over the semiconductor layer, a recess formed in the dielectric layer, and a layer of a first metal disposed between the dielectric layer and the semiconductor layer, the layer of the first metal being at a bottom of the recess, the halogen-containing catalyst modifying a surface of the layer of the first metal; after treating the substrate with the halogen-containing catalyst, treating the substrate with a molecular inhibitor (MI), the MI covering sidewalls of the dielectric layer in the recess; depositing a second metal over the modified surface of the layer of the first metal in the recess, where the MI covering the sidewalls prevents deposition of the second metal on the dielectric layer.

公开(公告)号：US11152260B2

公开(公告)日：2021-10-19

申请号：US16574672

申请日：2019-09-18

Applicant: TOKYO ELECTRON LIMITED

Inventor： Tadahiro Ishizaka

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/67

Abstract: An embedding method includes: removing a metal oxide film at a surface of a metal layer from a substrate that includes the metal layer on a bottom of a recess formed in an insulating layer; covering the surface of the metal layer by embedding ruthenium in the recess from the bottom of the recess; forming a ruthenium liner film in the recess; and further embedding ruthenium in the recess in which the liner film is formed.