公开(公告)号：US20180108518A1

公开(公告)日：2018-04-19

申请号：US15783048

申请日：2017-10-13

Applicant: Tokyo Electron Limited

Inventor： Naotaka Noro ,  Toshio Hasegawa ,  Tamaki Takeyama ,  Shinya Iwashita ,  Katsuhito Hirose

IPC: H01J37/32 ,  C23C16/50 ,  C23C16/455 ,  C23C16/44

CPC classification number: H01J37/32862 ,  C23C16/4405 ,  C23C16/4412 ,  C23C16/455 ,  C23C16/45542 ,  C23C16/45565 ,  C23C16/4586 ,  C23C16/50 ,  C23C16/505 ,  H01J37/3244

Abstract: A film forming apparatus 1 includes a plasma generating mechanism 47 commonly used for plasmarizing a processing gas and a cleaning gas supplied into a processing vessel 11 in which a vacuum atmosphere is formed; an exhaust device 17 configured to evacuate an exhaust line 61 connected to a processing gas discharge unit 43 while the plasmarization of the cleaning gas is being performed by the plasma generating mechanism 47; a tank 62 provided at the exhaust line 61; and a valve V2 which is provided at the exhaust line 61 between the tank 62 and the processing gas discharge unit 43. The valve V2 is configured to be closed to reduce an internal pressure of the tank 62 and opened to attract the plasmarized cleaning gas into the tank 62 from a processing space 40 through the processing gas discharge unit 43.

公开(公告)号：US11387112B2

公开(公告)日：2022-07-12

申请号：US16587760

申请日：2019-09-30

Applicant: TOKYO ELECTRON LIMITED

Inventor： Koichi Takatsuki ,  Tadahiro Ishizaka ,  Mikio Suzuki ,  Toshio Hasegawa

IPC: H01L21/311 ,  H01L21/285 ,  C23C16/455 ,  C23C16/02 ,  C23C16/06 ,  H01L21/768

Abstract: There is provided a method of performing a surface processing on a substrate having a metal layer formed on a bottom portion of a recess formed in an insulating film, the method including: supplying a halogen-containing gas into a processing chamber in which the substrate is loaded; and removing a metal oxide from the bottom portion of the recess using the halogen-containing gas.

公开(公告)号：US10535528B2

公开(公告)日：2020-01-14

申请号：US15730127

申请日：2017-10-11

Applicant: TOKYO ELECTRON LIMITED

Inventor： Naoki Shindo ,  Toshio Hasegawa ,  Naotaka Noro ,  Miyako Kaneko

IPC: H01L21/308 ,  H01L21/02

Abstract: A method for forming a titanium oxide film on a substrate to be processed, which has a silicon portion on a surface thereof, the method including: forming a first titanium oxide film on the surface of the substrate to be processed, which includes the silicon portion, by means of thermal ALD by alternately supplying a titanium-containing gas and a gas containing hydrogen and oxygen serving as an oxidizing agent in a first stage; and forming a second titanium oxide film on the first titanium oxide film by means of plasma ALD by alternately supplying a titanium-containing gas and plasma of an oxygen-containing gas as an oxidizing agent in a second stage.

公开(公告)号：US10361366B2

公开(公告)日：2019-07-23

申请号：US16054699

申请日：2018-08-03

Applicant: Tokyo Electron Limited

Inventor： Takahiro Hakamata ,  Genji Nakamura ,  Sara Aoki ,  Toshio Hasegawa ,  Takamichi Kikuchi

IPC: H01L45/00 ,  G11C13/00 ,  H01L41/08

Abstract: A plurality of embodiments for ReRAM devices and method of making are described. According to one embodiment, the ReRAM device includes a first electrode film formed on a substrate, a metal oxide film with oxygen vacancies formed on a first electrode film, a conformal TiAlC film, oxidized by diffused oxygen atoms from the metal oxide film, formed on the metal oxide film, and a second electrode film formed on the TiAlC film. According to another embodiment, the ReRAM device includes a pair of vertical metal oxide films, a pair of vertical conformal TiAlC films formed on the pair of vertical metal oxide films, the pair of vertical conformal TiAlC films oxidized by diffused oxygen atoms from the pair of vertical metal oxide films, and an electrode film formed between the pair of vertical conformal TiAlC films.

公开(公告)号：US20190088475A1

公开(公告)日：2019-03-21

申请号：US16132729

申请日：2018-09-17

Applicant: Tokyo Electron Limited

Inventor： Shinya Iwashita ,  Takamichi Kikuchi ,  Naotaka Noro ,  Toshio Hasegawa ,  Tsuyoshi Moriya

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/455 ,  C23C16/26

Abstract: Disclosed is a film forming method including forming a metal oxide film on a base film by alternately supplying a metal-containing gas and a plasmatized oxidizing gas. The metal-containing gas is changed from a first metal-containing gas having no halogen to a second metal-containing gas different from the first metal-containing gas during the film forming of the metal oxide film.

公开(公告)号：US20230054125A1

公开(公告)日：2023-02-23

申请号：US17406612

申请日：2021-08-19

Applicant: Tokyo Electron Limited

Inventor： Choong-man Lee ,  Soo Doo Chae ,  Angelique Raley ,  Qiaowei Lou ,  Toshio Hasegawa ,  Yoshihiro Kato

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311

Abstract: A method for fabricating a semiconductor device is described that includes forming a base layer over a top layer of a substrate, the base layer includes a silicon based dielectric having a thickness less than or equal to 5 nm and greater than or equal to 0.5 nm; forming a photoresist layer over the base layer, the photoresist including a first side and an opposite second side; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side; exposing a second portion of the photoresist layer with a pattern of electron flux from the second side, the electron flux being directed into the photoresist layer from the base layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; and transferring the pattern of the patterned photoresist layer to the base layer and the top layer.

公开(公告)号：US09698020B2

公开(公告)日：2017-07-04

申请号：US14918503

申请日：2015-10-20

Applicant: Tokyo Electron Limited

Inventor： Genji Nakamura ,  Toshio Hasegawa

IPC: H01L21/3213 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L21/8238

CPC classification number: H01L21/28088 ,  H01L21/321 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A method of forming a semiconductor device is disclosed in various embodiments. The method includes providing a substrate containing first and second device regions, and a high-k film on the substrate, depositing a metal nitride gate electrode film on the high-k film, forming a metal-containing gate electrode film on the metal nitride gate electrode film in the second device region but not in the first device region, and depositing a Si-based cap layer on the metal-containing gate electrode film in the second device region and on the metal nitride gate electrode film in the first device region.

公开(公告)号：US09607888B2

公开(公告)日：2017-03-28

申请号：US14613086

申请日：2015-02-03

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Toshio Hasegawa ,  Tadahiro Ishizaka ,  Manabu Oie ,  Fumitaka Amano ,  Steven Consiglio ,  Cory Wajda ,  Kaoru Maekawa ,  Gert J. Leusink

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  C23C16/04 ,  C23C16/34

CPC classification number: H01L21/76846 ,  C23C16/045 ,  C23C16/34 ,  H01L21/28562 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.

公开(公告)号：US20160111290A1

公开(公告)日：2016-04-21

申请号：US14918503

申请日：2015-10-20

Applicant: Tokyo Electron Limited

Inventor： Genji Nakamura ,  Toshio Hasegawa

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L21/28088 ,  H01L21/321 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A method of forming a semiconductor device is disclosed in various embodiments. The method includes providing a substrate containing first and second device regions, and a high-k film on the substrate, depositing a metal nitride gate electrode film on the high-k film, forming a metal-containing gate electrode film on the metal nitride gate electrode film in the second device region but not in the first device region, and depositing a Si-based cap layer on the metal-containing gate electrode film in the second device region and on the metal nitride gate electrode film in the first device region.

Abstract translation: 在各种实施例中公开了形成半导体器件的方法。 该方法包括提供含有第一和第二器件区的衬底和在衬底上的高k膜，在高k膜上沉积金属氮化物栅电极膜，在金属氮化物栅上形成含金属的栅极电极膜 在第二器件区域中而不是第一器件区域中的电极膜，并且在第二器件区域中的含金属的栅电极膜上和第一器件区域中的金属氮化物栅电极膜上沉积Si基覆盖层。

公开(公告)号：US08846474B2

公开(公告)日：2014-09-30

申请号：US13632101

申请日：2012-09-30

Applicant: Tokyo Electron Limited

Inventor： Genji Nakamura ,  Toshio Hasegawa

IPC: H01L21/283

CPC classification number: H01L21/823842

Abstract: Embodiments of the invention provide dual workfunction semiconductor devices and methods for manufacturing thereof. According to one embodiment, the method includes providing a substrate containing first and second device regions, depositing a dielectric film on the substrate, and forming a first metal-containing gate electrode film on the dielectric film, wherein a thickness of the first metal-containing gate electrode film is less over the first device region than over the second device region. The method further includes depositing a second metal-containing gate electrode film on the first metal-containing gate electrode film, patterning the second metal-containing gate electrode film, the first metal-containing gate electrode film, and the dielectric film to form a first gate stack above the first device region and a second gate stack above the second device region.

Abstract translation: 本发明的实施例提供了双功能半导体器件及其制造方法。 根据一个实施例，该方法包括提供含有第一和第二器件区域的衬底，在衬底上沉积电介质膜，以及在电介质膜上形成第一含金属栅极电极膜，其中第一含金属的 栅极电极膜比第二器件区域小于第一器件区域。 该方法还包括在第一含金属栅极电极膜上沉积第二含金属的栅电极膜，使第二含金属栅电极膜，第一含金属栅极电极膜和电介质膜图案化，以形成第一含金属栅极电极膜 栅极堆叠在第一器件区域上方，第二栅极堆叠在第二器件区域上方。