公开(公告)号：US20230411142A1

公开(公告)日：2023-12-21

申请号：US18198355

申请日：2023-05-17

Applicant: Tokyo Electron Limited

Inventor： Ryota Yonezawa ,  Kai-Hung Yu ,  Tadahiro Ishizaka ,  Atsushi Gomi ,  Hidenao Suzuki

IPC: H01L21/02 ,  H01L21/3205

CPC classification number: H01L21/02068 ,  H01L21/32051

Abstract: Improved process flows and methods are provided for processing a semiconductor substrate have exposed dielectric and metal-containing surfaces. More specifically, improved process flows and methods are provided for pre-cleaning the metal-containing surfaces prior to depositing a metal material onto the metal-containing surfaces. Hot vapor-phase etching is used to remove a native oxide film from the metal-containing surfaces. Prior to hot vapor-phase etching, the semiconductor substrate is exposed to a first silicon-containing gas to deposit an inhibitor film onto the exposed dielectric and metal-containing surfaces. The inhibitor film protects the dielectric surfaces while the native oxide film is being removed via the hot vapor-phase etching. In some embodiments, the semiconductor substrate is exposed to a second silicon-containing gas, after hot vapor-phase etching, to remove residues of the hot vapor-phase etching process from the pre-cleaned metal-containing surfaces.

公开(公告)号：US20230343592A1

公开(公告)日：2023-10-26

申请号：US17660111

申请日：2022-04-21

Applicant: Tokyo Electron Limited

Inventor： Shihsheng Chang ,  Andrew Metz ,  Yun Han ,  Ya-Ming Chen ,  Kai-Hung Yu ,  Eric Chih-Fang Liu

IPC: H01L21/033

CPC classification number: H01L21/0332

Abstract: A method of fabricating an amorphous carbon layer (ACL) mask includes forming an ACL on an underlying layer. The ACL includes a soft ACL portion that has a first hardness and a hard ACL portion that has a second hardness. The soft ACL portion underlies the hard ACL portion. The second hardness is greater than the first hardness. The method further includes forming a patterned layer over the ACL and forming an ACL mask by etching through both the soft ACL portion and the hard ACL portion of the ACL to expose the underlying layer using the patterned layer as an etch mask. Forming the ACL may include depositing one or both of the soft ACL portion and the hard ACL portion. Processing conditions may also be varied while forming the ACL to create a hardness gradient that transitions from softer to harder.

公开(公告)号：US11621190B2

公开(公告)日：2023-04-04

申请号：US17334389

申请日：2021-05-28

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  David O'Meara ,  Nicholas Joy ,  Gyanaranjan Pattanaik ,  Robert Clark ,  Kandabara Tapily ,  Takahiro Hakamata ,  Cory Wajda ,  Gerrit Leusink

IPC: H01L21/768 ,  H01L21/02

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

公开(公告)号：US11594451B2

公开(公告)日：2023-02-28

申请号：US17140310

申请日：2021-01-04

Applicant: Tokyo Electron Limited

Inventor： Robert Clark ,  Kandabara Tapily ,  Kai-Hung Yu

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/66 ,  H01L21/677 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  G05B13/02 ,  G05B19/418 ,  C23C14/24 ,  C23C14/34 ,  H01J37/32

Abstract: A method of preparing a self-aligned via on a semiconductor workpiece includes using an integrated sequence of processing steps executed on a common manufacturing platform hosting a plurality of processing modules including one or more film-forming modules, one or more etching modules, and one or more transfer modules. The integrated sequence of processing steps include receiving the workpiece into the common manufacturing platform, the workpiece having a pattern of metal features in a dielectric layer wherein exposed surfaces of the metal features and exposed surfaces of the dielectric layer together define an upper planar surface; selectively etching the metal features to form a recess pattern by recessing the exposed surfaces of the metal features beneath the exposed surfaces of the dielectric layer using one of the one or more etching modules; and depositing an etch stop layer over the recess pattern using one of the one or more film-forming modules.

公开(公告)号：US10923394B2

公开(公告)日：2021-02-16

申请号：US16357724

申请日：2019-03-19

Applicant: Tokyo Electron Limited

Inventor： Robert Clark ,  Kandabara Tapily ,  Kai-Hung Yu

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/67 ,  H01L21/66 ,  H01L21/677 ,  H01L21/285 ,  H01L21/311 ,  G05B13/02 ,  G05B19/418 ,  C23C14/24 ,  C23C14/34 ,  H01J37/32

Abstract: A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.

公开(公告)号：US20190288004A1

公开(公告)日：2019-09-19

申请号：US16357893

申请日：2019-03-19

Applicant: TOKYO ELECTRON LIMITED

Inventor： Jeffrey SMITH ,  Anton deVilliers ,  Kandabara Tapily ,  Jodi Grzeskowiak ,  Kai-Hung Yu

IPC: H01L27/118 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L21/768

Abstract: A semiconductor device includes a plurality of first sources/drains and a plurality of first source/drain (S/D) contacts formed over the first sources/drains. The device also includes a plurality of first dielectric caps. Each of the plurality of first dielectric caps is positioned over a respective first S/D contact to cover a top portion and at least a part of side portions of the respective first S/D contact. The device also includes a plurality of second sources/drains and a plurality of second S/D contacts that are staggered over the plurality of first S/D contacts so as to form a stair-case configuration. A plurality of second dielectric caps are formed over the plurality of second S/D contacts. Each of the plurality of second dielectric caps is positioned over a respective second S/D contact to cover a top portion and at least a part of side portions of the respective second S/D contact.

公开(公告)号：US20190103363A1

公开(公告)日：2019-04-04

申请号：US16147928

申请日：2018-10-01

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Nicholas Joy ,  Eric Chih Fang Liu ,  David L. O'Meara ,  David Rosenthal ,  Masanobu Igeta ,  Cory Wajda ,  Gerrit J. Leusink

IPC: H01L23/532 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/768 ,  C23C16/455 ,  C23C16/16 ,  C23C16/56

Abstract: A method is provided for void-free Ru metal filling of features in a substrate. The method includes providing a substrate containing features, depositing a Ru metal layer in the features, removing the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the features at a higher rate than on the field area. According to one embodiment, the additional Ru metal is deposited until the features are fully filled with Ru metal.

公开(公告)号：US10157784B2

公开(公告)日：2018-12-18

申请号：US15428749

申请日：2017-02-09

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Manabu Oie ,  Kaoru Maekawa ,  Cory Wajda ,  Gerrit J. Leusink ,  Yuuki Kikuchi ,  Hiroaki Kawasaki ,  Hiroyuki Nagai

IPC: H01L21/285 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Methods for integration of conformal barrier layers and Ru metal liners with Cu metallization in semiconductor manufacturing are described in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a barrier layer in the recessed feature, depositing a Ru metal liner on the barrier layer, and exposing the substrate to an oxidation source gas to oxidize the barrier layer through the Ru metal liner. The method further includes filling the recessed feature with CuMn metal using an ionized physical vapor deposition (IPVD) process, heat-treating the substrate to diffuse Mn from the CuMn metal to the oxidized barrier layer, and reacting the diffused Mn with the oxidized barrier layer to form a Mn-containing diffusion barrier.

公开(公告)号：US20240153781A1

公开(公告)日：2024-05-09

申请号：US18385522

申请日：2023-10-31

Applicant: Tokyo Electron Limited

Inventor： Hisashi Higuchi ,  Kai-Hung Yu ,  Cory Wajda ,  Gyanaranjan Pattanaik ,  Kandabara Tapily ,  Gerrit Leusink ,  Robert Clark

IPC: H01L21/3213 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/32136 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02337 ,  H01L21/31122

Abstract: Embodiments of methods are provided for thermal dry etching of a ruthenium (Ru) metal layer. In the disclosed embodiments, a substrate containing a Ru metal layer formed thereon is exposed to a gas pulse sequence, while the substrate is held at a relatively high substrate temperature (e.g., a temperature greater than or equal to about 160° C.), to provide thermal etching of the Ru metal layer. As described further herein, the gas pulse sequence may generally include a plurality of gas pulses, which are supplied to the substrate sequentially with substantially no overlap between gas pulses. The gas pulses supplied to the substrate form: (i) volatile reaction products that are vaporized from the Ru surface, and (ii) non-volatile oxide surface layers that are removed from the Ru surface by the next gas pulse, resulting in atomic layer etching (ALE) of the Ru metal layer.

公开(公告)号：US20220301930A1

公开(公告)日：2022-09-22

申请号：US17688343

申请日：2022-03-07

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Shihsheng Chang ,  Ying Trickett ,  Eric Chih-Fang Liu ,  Yun Han ,  Henan Zhang ,  Cory Wajda ,  Robert D. Clark ,  Gerrit J. Leusink ,  Gyanaranjan Pattanaik ,  Hiroaki Niimi

IPC: H01L21/768

Abstract: A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, forming a nucleation enhancement layer on a sidewall of the first layer in the recessed feature and depositing a metal layer in the recessed feature by vapor phase deposition, where the metal layer is deposited on the second layer and on the nucleation enhancement layer. An initial metal layer may be selectively formed on the second layer in the recessed feature before forming the nucleation enhancement layer.