公开(公告)号：US20150221550A1

公开(公告)日：2015-08-06

申请号：US14613086

申请日：2015-02-03

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Toshio Hasegawa ,  Tadahiro Ishizaka ,  Manabu Oie ,  Fumitaka Amano ,  Steven Consiglio ,  Cory Wajda ,  Kaoru Maekawa ,  Gert J. Leusink

IPC: H01L21/768

CPC classification number: H01L21/76846 ,  C23C16/045 ,  C23C16/34 ,  H01L21/28562 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.

Abstract translation: 在几个实施例中公开了用于整合用于半导体器件的窄凹陷特征的Cu填充的Ru衬垫的阻挡层的原子层沉积（ALD）和化学气相沉积（CVD）的方法。 根据一个实施方案，该方法包括提供含有凹陷特征的基底，在凹陷特征中通过ALD沉积共形阻挡层，其中阻挡层包含TaN或TaAlN，通过CVD在阻挡层上沉积共形Ru衬垫;以及 用Cu金属填充凹陷特征。

公开(公告)号：US09607888B2

公开(公告)日：2017-03-28

申请号：US14613086

申请日：2015-02-03

Applicant: Tokyo Electron Limited

Inventor： Kai-Hung Yu ,  Toshio Hasegawa ,  Tadahiro Ishizaka ,  Manabu Oie ,  Fumitaka Amano ,  Steven Consiglio ,  Cory Wajda ,  Kaoru Maekawa ,  Gert J. Leusink

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  C23C16/04 ,  C23C16/34

CPC classification number: H01L21/76846 ,  C23C16/045 ,  C23C16/34 ,  H01L21/28562 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for integration of atomic layer deposition (ALD) of barrier layers and chemical vapor deposition (CVD) of Ru liners for Cu filling of narrow recessed features for semiconductor devices are disclosed in several embodiments. According to one embodiment, the method includes providing a substrate containing a recessed feature, depositing a conformal barrier layer by ALD in the recessed feature, where the barrier layer contains TaN or TaAlN, depositing a conformal Ru liner by CVD on the barrier layer, and filling the recessed feature with Cu metal.

公开(公告)号：US09558962B2

公开(公告)日：2017-01-31

申请号：US14823363

申请日：2015-08-11

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Fumitaka Amano

IPC: H01L21/311 ,  H01L21/02 ,  H01L29/16 ,  H01L21/28 ,  H01L29/161 ,  H01L29/51

CPC classification number: H01L21/31116 ,  H01J37/32192 ,  H01L21/0206 ,  H01L21/02252 ,  H01L21/02337 ,  H01L21/28238 ,  H01L21/28255 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/31122 ,  H01L21/321 ,  H01L29/16 ,  H01L29/161 ,  H01L29/513 ,  H01L29/517

Abstract: A method for passivating a surface of a semiconductor substrate with fluorine-based layer to protect the surface against oxidation and allow longer queue times. According to one embodiment, the method includes providing a substrate having an oxidized layer formed thereon, replacing the oxidized layer with a fluorine-based layer, exposing the fluorine-based layer to an oxidizing atmosphere, where the fluorine-based layer protects the substrate against oxidation by the oxidizing atmosphere, and removing the fluorine-based layer from the substrate using a plasma process. According to another embodiment, the method includes providing a passivated substrate in a vacuum processing tool, the passivated substrate having a fluorine-based layer thereon that is effective for protecting the passivated substrate against oxidation by an oxidizing atmosphere, removing the fluorine-based layer from the passivated substrate using a microwave plasma process in the vacuum processing tool, thereby forming a clean substrate, and processing the clean substrate under vacuum conditions.

Abstract translation: 一种用氟基层钝化半导体衬底的表面以保护表面免受氧化并允许更长的排队时间的方法。 根据一个实施例，该方法包括提供其上形成有氧化层的基板，用氟基层代替氧化层，将氟基层暴露于氧化气氛，其中氟基层保护基板免受 通过氧化气氛进行氧化，使用等离子体处理从基板除去氟系层。 根据另一实施例，该方法包括在真空处理工具中设置钝化衬底，钝化衬底上具有氟基层，其有效地保护被钝化衬底免受氧化气氛的氧化，从氟基层除去氟基层 在真空处理工具中使用微波等离子体工艺的钝化衬底，从而形成清洁衬底，并在真空条件下处理清洁衬底。

公开(公告)号：US20160049309A1

公开(公告)日：2016-02-18

申请号：US14823363

申请日：2015-08-11

Applicant: Tokyo Electron Limited

Inventor： Kandabara N. Tapily ,  Fumitaka Amano

IPC: H01L21/311 ,  H01L29/161 ,  H01L29/16 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/31116 ,  H01J37/32192 ,  H01L21/0206 ,  H01L21/02252 ,  H01L21/02337 ,  H01L21/28238 ,  H01L21/28255 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/31122 ,  H01L21/321 ,  H01L29/16 ,  H01L29/161 ,  H01L29/513 ,  H01L29/517

Abstract: A method for passivating a surface of a semiconductor substrate with fluorine-based layer to protect the surface against oxidation and allow longer queue times. According to one embodiment, the method includes providing a substrate having an oxidized layer formed thereon, replacing the oxidized layer with a fluorine-based layer, exposing the fluorine-based layer to an oxidizing atmosphere, where the fluorine-based layer protects the substrate against oxidation by the oxidizing atmosphere, and removing the fluorine-based layer from the substrate using a plasma process. According to another embodiment, the method includes providing a passivated substrate in a vacuum processing tool, the passivated substrate having a fluorine-based layer thereon that is effective for protecting the passivated substrate against oxidation by an oxidizing atmosphere, removing the fluorine-based layer from the passivated substrate using a microwave plasma process in the vacuum processing tool, thereby forming a clean substrate, and processing the clean substrate under vacuum conditions.

Abstract translation: 一种用氟基层钝化半导体衬底的表面以保护表面免受氧化并允许更长的排队时间的方法。 根据一个实施例，该方法包括提供其上形成有氧化层的基板，用氟基层代替氧化层，将氟基层暴露于氧化气氛，其中氟基层保护基板免受 通过氧化气氛进行氧化，使用等离子体处理从基板除去氟系层。 根据另一实施例，该方法包括在真空处理工具中设置钝化衬底，钝化衬底上具有氟基层，其有效地保护被钝化衬底免受氧化气氛的氧化，从氟基层除去氟基层 在真空处理工具中使用微波等离子体工艺的钝化衬底，从而形成清洁衬底，并在真空条件下处理清洁衬底。