公开(公告)号：EP3249696A1

公开(公告)日：2017-11-29

申请号：EP17171963.6

申请日：2017-05-19

申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

发明人： HONG, Zhongshan ,  HUA, Kelu ,  PENG, Jin

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/265 ,  H01L21/3086 ,  H01L21/324 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/36 ,  H01L29/66553 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7854

摘要： A semiconductor structure and a method for fabricating a semiconductor structure are provided. The method includes forming one or more fins on a substrate, wherein each fin includes a first sidewall and a second sidewall opposing each other. The method also includes forming a sacrificial layer over the fin. Further, the method also includes performing a first ion implantation process on the first sidewall and a top of the fin, and performing a second ion implantation process on the second sidewall and the top of the fin.

摘要翻译： 提供了一种半导体结构和一种用于制造半导体结构的方法。 该方法包括在衬底上形成一个或多个鳍片，其中每个鳍片包括彼此相对的第一侧壁和第二侧壁。 该方法还包括在鳍上形成牺牲层。 进一步的，所述方法还包括在所述鳍片的第一侧壁和顶部进行第一离子注入工艺，并在所述鳍片的第二侧壁和顶部进行第二离子注入工艺。

公开(公告)号：EP3050106A4

公开(公告)日：2017-05-10

申请号：EP13894350

申请日：2013-09-27

申请人： INTEL CORP

发明人： PARK JOODONG ,  BHIMARASETTI GOPINATH ,  RAMASWAMY RAHUL ,  JAN CHIA-HONG ,  HAFEZ WALID M ,  YEH JENG-YA D ,  TSAI CURTIS

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/10826 ,  H01L27/10808 ,  H01L27/10879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7854

摘要： Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors for eDRAM are described. For example, a semiconductor device includes a semiconductor fin disposed above a substrate and including a narrow fin region disposed between two wide fin regions. A gate electrode stack is disposed conformal with the narrow fin region of the semiconductor fin, the gate electrode stack including a gate electrode disposed on a gate dielectric layer. The gate dielectric layer includes a lower layer and an upper layer, the lower layer composed of an oxide of the semiconductor fin. A pair of source/drain regions is included, each of the source/drain regions disposed in a corresponding one of the wide fin regions.

摘要翻译： 描述了用于嵌入式动态随机存取存储器（eDRAM）的低泄漏非平面存取晶体管和制造用于eDRAM的低泄漏非平面存取晶体管的方法。 例如，半导体器件包括设置在衬底上方的半导体鳍片，并包括设置在两个宽鳍片区域之间的窄鳍片区域。 栅电极叠层被布置为与半导体鳍的窄鳍状物区共形，该栅电极叠层包括设置在栅电介质层上的栅电极。 栅介质层包括下层和上层，下层由半导体鳍状物的氧化物构成。 包括一对源极/漏极区域，每个源极/漏极区域设置在对应的一个宽鳍片区域中。

公开(公告)号：EP2334848A1

公开(公告)日：2011-06-22

申请号：EP09756003.1

申请日：2009-10-09

申请人： Ecole Polytechnique ,  Centre National de la Recherche Scientifique

发明人： ROCA I CABARROCAS, Pere ,  YU, Linwei

IPC分类号： C30B11/12 ,  C30B29/06 ,  C30B29/60 ,  C30B29/08 ,  H01L29/06 ,  H01L29/786

CPC分类号： H01L21/02653 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C30B9/10 ,  C30B29/06 ,  C30B29/08 ,  C30B29/52 ,  C30B29/605 ,  H01L21/02403 ,  H01L21/02414 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02645 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/161 ,  H01L29/24 ,  H01L29/6675 ,  H01L29/66772 ,  H01L29/7854 ,  H01L29/78603 ,  H01L29/78696 ,  H01L51/0048

摘要： The invention relates to a method for making semiconductor nanowires (5) on a substrate (1) including a metal oxide layer (2), said method including the following steps: (a) exposing the metal oxide layer (2) to a hydrogen plasma (11) capable of triggering a reduction of the layer (2) and of generating metal nanodrops (3) having a radius (Rm) at the surface of the metal oxide layer (2); (b) plasma-depositing a thin layer (4) of a semiconductor material on the metal oxide layer (2), said thin layer (4) having a thickness (H3) suitable for covering the metal nanodrops (3); (c) and thermal annealing at a temperature T sufficient for activating a side growth of nanowires (5) by catalysis of the material deposited as a thin layer (4) from the metal nanodrops (3). The invention also relates to the nanowires (5) obtained by the method of the invention, and to nanometric transistors including a semiconductor nanowire (5), e.g. a silicon nanowire (SiNW) for forming a semiconductor link between the source (16), the drain (17), and the gate (18).

公开(公告)号：EP2257974A1

公开(公告)日：2010-12-08

申请号：EP09714517.1

申请日：2009-02-17

申请人： NXP B.V.

发明人： CURATOLA, Gilberto ,  AGARWAL, Prabhat ,  VAN DAL, Mark, J., H. ,  MADAKASIRA, Vijayaraghavan

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/7854 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775

摘要： A method of manufacturing a semiconductor device is disclosed comprising providing an insulating carrier (10) such as an oxide wafer; providing a channel structure (20) between a source structure (12) and a drain structure (14) on said carrier (10); selectively removing a part of the channel structure (20), thereby forming a recess (22) between the channel structure (20) and the carrier (10); exposing the device to an annealing step such that the channel structure (20') obtains a substantially cylindrical shape; forming a confinement layer (40) surrounding the substantially cylindrical channel structure (20'); growing an oxide layer (50) surrounding the confinement layer (40); and forming a gate structure (60) surrounding the oxide layer (50). The substantially cylindrical channel structure 20' may comprise the semiconductor layer 30. A corresponding semiconductor device is also disclosed.

摘要翻译： 公开了一种制造半导体器件的方法，包括提供诸如氧化物晶片的绝缘载体（10） 在所述载体（10）上的源极结构（12）和漏极结构（14）之间提供沟道结构（20）; 选择性地去除所述通道结构（20）的一部分，从而在所述通道结构（20）和所述载体（10）之间形成凹槽（22）; 使器件暴露于退火步骤，使得沟道结构（20'）获得基本上圆柱形的形状; 形成围绕所述基本圆柱形的通道结构（20'）的约束层（40）; 围绕所述约束层（40）生长氧化物层（50）; 以及形成围绕氧化物层（50）的栅极结构（60）。 大致圆柱形的沟道结构20'可以包括半导体层30.还公开了相应的半导体器件。

公开(公告)号：EP1581968A1

公开(公告)日：2005-10-05

申请号：EP02808339.2

申请日：2002-12-20

申请人： International Business Machines Corporation

发明人： RANKIN, Jed, H. ,  ABADEER, Wagdi, W. ,  BROWN, Jeffrey, S. ,  CHATTY, Kiran, V. ,  TONTI, William, R. ,  GAUTHIER, Robert, J., Jr. ,  FRIED, David, M.

IPC分类号： H01L21/82 ,  H01L21/44

CPC分类号： H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t-114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).

公开(公告)号：EP3493256A2

公开(公告)日：2019-06-05

申请号：EP18203574.1

申请日：2018-10-30

申请人： INTEL Corporation

发明人： YEOH, Andrew W. ,  MADHAVAN, Atul ,  HATTENDORF, Michael L. ,  AUTH, Christopher P.

IPC分类号： H01L23/528 ,  H01L21/8238 ,  H01L21/768

CPC分类号： H01L23/5283 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0924 ,  H01L27/1104 ,  H01L28/24 ,  H01L29/0847 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7854

摘要： Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines in and spaced apart by an ILD layer. The plurality of conductive interconnect lines includes a first interconnect line, and a second interconnect line immediately adjacent the first interconnect line and having a width different than a width of the first interconnect line. A third interconnect line is immediately adjacent the second interconnect line. A fourth interconnect line is immediately adjacent the third interconnect line and has a width the same as the width of the second interconnect line. A fifth interconnect line is immediately adjacent the fourth interconnect line and has a width the same as the width of the first interconnect line.

公开(公告)号：EP3316288A1

公开(公告)日：2018-05-02

申请号：EP17198884.3

申请日：2017-10-27

申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

发明人： LI, Yong

IPC分类号： H01L21/8238 ,  H01L21/268

CPC分类号： H01L29/7854 ,  H01L21/268 ,  H01L21/823814 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/78621

摘要： A method for manufacturing a semiconductor device includes providing a substrate structure having PMOS and NMOS regions. The PMOS region includes a first region, a first gate structure (202) on the first region, and first source and drain regions (203, 204) on opposite sides of the first gate structure. The NMOS region includes a second region and a second gate structure (206) on the second region. The method also includes introducing a p-type dopant into the first source and drain regions, performing a first annealing, forming second source and drain regions (401, 402) on opposite sides of the second gate structure, introducing an n-type dopant into the second source and drain regions, and performing a second annealing. The method satisfies thermal budget requirements of forming PMOS and NMOS devices, thereby enabling a better diffusion of the p-type dopant into the source and drain regions of the PMOS device without affecting the performance of the NMOS device.

摘要翻译： 一种用于制造半导体器件的方法包括提供具有PMOS和NMOS区域的衬底结构。 PMOS区域包括第一区域，第一区域上的第一栅极结构（202）以及第一栅极结构的相对侧上的第一源极区域和漏极区域（203,204）。 NMOS区域包括第二区域和第二区域上的第二栅极结构（206）。 该方法还包括将p型掺杂剂引入到第一源极和漏极区域中，执行第一退火，在第二栅极结构的相对侧上形成第二源极和漏极区域（401,402），将n型掺杂剂引入 第二源极和漏极区域，并且执行第二退火。 该方法满足形成PMOS和NMOS器件的热预算要求，从而能够在不影响NMOS器件的性能的情况下更好地将p型掺杂剂扩散到PMOS器件的源极和漏极区域中。

公开(公告)号：EP2175492A4

公开(公告)日：2017-08-23

申请号：EP08710456

申请日：2008-02-22

申请人： GODO KAISHA IP BRIDGE 1

发明人： SASAKI YUICHIRO ,  OKASHITA KATSUMI ,  NAKAMOTO KEIICHI ,  KANADA HISATAKA ,  MIZUNO BUNJI

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L21/336

CPC分类号： H01L29/7854 ,  H01L29/66803

公开(公告)号：EP1581968A4

公开(公告)日：2007-04-18

申请号：EP02808339

申请日：2002-12-20

申请人： IBM

发明人： RANKIN JED H ,  ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J JR ,  FRIED DAVID M

IPC分类号： H01L23/525 ,  H01L21/82 ,  H01L21/84 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t-114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).

公开(公告)号：EP1566844A3

公开(公告)日：2006-04-05

申请号：EP05250932.0

申请日：2005-02-18

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Shigenobu, Maeda, A-2601 Royal Palace Houseville ,  Yang, Jeong-hwan, 712-204, Salgugol 7-danji ,  Choi, Jung-a, 108-1802, Samgeo Maeul Samsung

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7854 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66795

摘要： In a semiconductor capable of reducing NBTI and a method for manufacturing the same, a multi-gate transistor includes an active region, gate dielectric, channels in the active region, and gate electrodes, and is formed on a semiconductor wafer. The active region has a top and side surfaces, and is oriented in a first direction. The gate dielectric is formed on the top and side surfaces of the active region. The channels are formed in the top and side surfaces of the active region. The gate electrodes are formed on the gate dielectric corresponding to the channels and aligned perpendicular to the active region such that current flows in the first direction. In one aspect of the invention, an SOI layer having a second orientation indicator in a second direction is formed on a supporting substrate having a first orientation indicator in a first direction. A multi-gate transistor is formed on the SOI layer. The first direction and the second direction are the same, or the first direction is at 45 degrees with respect to the second direction. In another aspect of the invention, the intersection of the top and side surfaces of the active region are curved, further reducing NBTI. In another aspect of the invention, a multi-gate transistor is formed on a shallow trench isolation region of a bulk wafer.