公开(公告)号：EP4425196A1

公开(公告)日：2024-09-04

申请号：EP24157104.1

申请日：2024-02-12

申请人： STMicroelectronics International N.V.

发明人： TORTORA, Gianluca ,  BARONE, Mario

IPC分类号： G01R31/3185

CPC分类号： G01R31/318536

摘要： An integrated circuit is disclosed. The integrated circuit comprises a sequential logic circuit (20) and a circuit (204, 220) configured to change operation as a function of a subset of the state output signals (Q) provided by state flip-flops (202; 402) of the sequential logic circuit (20). A test circuit (300, 404, 406) is configured to determine whether a test mode signal (SCAN_MODE) is asserted and, when the test mode signal (SCAN_MODE) is asserted, write and read (TE, TI, TO) the content of the state flip-flops (202; 402) in order to test the operation of the sequential logic circuit (20).
In particular, the processing system (10) comprises also at least one storage circuit (408). Each storage circuit (408) is interposed between the circuit (204, 220) and a respective state output signal (Q), wherein each storage circuit (408) is configured to receive the respective state output signal (Q) and provide a modified state signal (Q') to the circuit (204, 220). Specifically, when the test mode signal (SCAN_MODE) is de-asserted, the storage circuit (408) provides the received state output signal (Q) in a transparent manner to the circuit (204, 220) and stores the received state output signal (Q) to a storage element (4082; 4086). Conversely, when the test mode signal (SCAN_MODE) is asserted, the storage circuit (408) provides the stored state output signal (Q') to the circuit (204, 220).

公开(公告)号：EP4390623A9

公开(公告)日：2024-09-04

申请号：EP23213652.3

申请日：2023-12-01

申请人： STMicroelectronics International N.V.

发明人： POLI, Salvatore ,  MARCHESE, Carmela

IPC分类号： G06F1/3203 ,  H02M1/36

CPC分类号： G06F1/3287

摘要： A microelectromechanical sensor device (1) has a detection structure (66) and an associated electronic circuitry (2), configured to receive, when the device is powered, an external power supply voltage (VDD) and provided with a voltage regulator (8) generating a regulated voltage (VREG) and with at least one voltage domain (6) powered by the regulated voltage. The electronic circuitry has a power supply management core (10), always powered by the external power supply voltage and which controls the voltage regulator to selectively interrupt the power supply of the voltage domain to implement: a first power-down condition wherein the voltage regulator is disabled; and a second power-down condition wherein the voltage regulator is enabled to power the aforementioned voltage domain through the regulated voltage, the first and the second power-down conditions being associated with absence of data acquisition by the sensor device. The power supply management core automatically enables the first or second power-down condition upon a first power-on of the sensor device, as a function of a configuration signal (Sconf), programmable, for example, during a factory calibration step.

公开(公告)号：EP4415042A2

公开(公告)日：2024-08-14

申请号：EP24154067.3

申请日：2024-01-26

申请人： STMicroelectronics International N.V.

发明人： TALLEDO; Jefferson Sismundo

IPC分类号： H01L23/495 ,  H01L21/56

CPC分类号： H01L23/49582 ,  H01L23/49524 ,  H01L21/561

摘要： An etched leadframe includes separated frame portions, where each frame portion includes an intermediate region interposed between lead and die pad regions. An integrated circuit die is mounted to each die pad region. A clip is mounted to each integrated circuit die, wherein the clip includes a lead mounting portion mounted to the lead region of an adjacent frame portion and a bridge portion extending over the intermediate region of the adjacent frame portion and mounted to the die pad region of the adjacent frame portion. A first cut made through the frame portion of each etched leadframe at the intermediate region separates the lead and die pad regions without severing the bridge portion of each clip. A conductive layer is plated on full sidewalls of the lead and die pad regions exposed by the first cut. A second cut is then made through the bridge portion of each clip.

公开(公告)号：EP4411735A1

公开(公告)日：2024-08-07

申请号：EP24153361.1

申请日：2024-01-23

申请人： STMicroelectronics International N.V.

发明人： BENHAMMADI, Jawad

IPC分类号： G11C13/00 ,  G11C29/42 ,  G06F11/10 ,  G06F12/02 ,  G06F3/06

CPC分类号： G11C13/0004 ,  G11C13/0023 ,  G06F3/0679 ,  G06F3/0664 ,  G11C29/42 ,  G11C13/0069 ,  G06F11/1048 ,  G06F3/0607

摘要： La présente description concerne un procédé d'émulation d'une mémoire EEPROM dans une mémoire à changement de phase (104) d'un circuit intégrant un microprocesseur, le procédé comprenant les étapes suivantes : définir une granularité d'écriture dans des lignes de la mémoire à changement de phase en fonction de la taille de paquets de données à écrire (EEelement1, EEelement2, EEelementS) ; associer à chaque paquet de données, un code premier correcteur d'erreur (ECC1, ECC2, ECC3) calculé par un programme (SW) exécuté par ledit microprocesseur ; et stocker les codes correcteurs d'erreur des paquets de données dans la même ligne que ces derniers.

公开(公告)号：EP4391465A2

公开(公告)日：2024-06-26

申请号：EP23213892.5

申请日：2023-12-04

申请人： STMicroelectronics International N.V.

发明人： GENNARI SANTORI, Valerio ,  CURINA, Carlo ,  BENDOTTI, Valerio ,  DE CAMPO, Nicola

IPC分类号： H04L25/49

CPC分类号： H04L25/4902

摘要： A receiver circuit (104') receives a differential signal (Vd) that includes positive and negative spikes. A first comparator (42) produces an intermediate set signal (COMPN) that includes a pulse at each positive spike of the differential signal, and a second comparator (44) produces an intermediate reset signal (COMPP) that includes a pulse at each negative spike of the differential signal. A sensing circuit (80) extracts a common-mode voltage signal (VCM,sense) from the differential signal and asserts a control signal (VC1, VC2) when the amplitude of the common-mode voltage signal exceeds a threshold (Vth+, Vth-). A logic circuit (81) asserts a masking signal (MASK) for a masking time interval in response to the control signal (VC1, VC2) being asserted, and de-asserts the masking signal in response to the masking time interval elapsing. The logic circuit produces (87) a corrected set signal (COMP'N) by passing the intermediate set signal (COMPN) when the masking signal (MASK) is de-asserted and masking the intermediate set signal (COMPN) when the masking signal (MASK) is de-asserted. The logic circuit produces (88) a corrected reset signal (COMP'P) by passing the intermediate reset signal (COMPP) when the masking signal (MASK) is de-asserted and masking the intermediate reset signal (COMPP) when the masking signal (MASK) is de-asserted. An output circuit (46) asserts an output signal (PWMRX) in response to a pulse detected in the corrected set signal (COMP'N) and de-asserts the output signal (PWMRX) in response to a pulse detected in the corrected reset signal (COMP'P).

公开(公告)号：EP4390623A1

公开(公告)日：2024-06-26

申请号：EP23213652.3

申请日：2023-12-01

申请人： STMicroelectronics International N.V.

发明人： POLI, Salvatore ,  MARCHESE, Carmela

IPC分类号： G06F1/3203 ,  H02M1/36

CPC分类号： G06F1/3203 ,  H02M1/36

摘要： A microelectromechanical sensor device (1) has a detection structure (66) and an associated electronic circuitry (2), configured to receive, when the device is powered, an external power supply voltage (VDD) and provided with a voltage regulator (8) generating a regulated voltage (VREG) and with at least one voltage domain (6) powered by the regulated voltage. The electronic circuitry has a power supply management core (10), always powered by the external power supply voltage and which controls the voltage regulator to selectively interrupt the power supply of the voltage domain to implement: a first power-down condition wherein the voltage regulator is disabled; and a second power-down condition wherein the voltage regulator is enabled to power the aforementioned voltage domain through the regulated voltage, the first and the second power-down conditions being associated with absence of data acquisition by the sensor device. The power supply management core automatically enables the first or second power-down condition upon a first power-on of the sensor device, as a function of a configuration signal (Sconf), programmable, for example, during a factory calibration step.

公开(公告)号：EP4386672A1

公开(公告)日：2024-06-19

申请号：EP23213874.3

申请日：2023-12-04

申请人： STMicroelectronics International N.V.

发明人： NICOLAS, Marina

IPC分类号： G06T7/254

CPC分类号： G06T7/254

摘要： La présente description concerne un procédé de détermination d'au moins un classificateur de mouvement global selon une première direction dans des images vidéo d'une scène, comprenant les étapes consistant à déterminer une image différentielle à partir de deux images vidéo ; sélectionner des pixels de l'image différentielle correspondant à des bords d'objets ; déterminer, pour chaque pixel sélectionné, au moins un classificateur de mouvement local selon la première direction au moins à une première ou deuxième valeur ; déterminer un premier indicateur de mouvement local selon la première direction qui dépend de la somme des classificateurs de mouvement local à la première valeur et un deuxième indicateur de mouvement local selon la première direction qui dépend de la somme des classificateurs de mouvement local à la deuxième valeur ; et déterminer le classificateur de mouvement global à partir de la comparaison des premier et deuxième indicateurs de mouvement local.

公开(公告)号：EP4383571A1

公开(公告)日：2024-06-12

申请号：EP23210398.6

申请日：2023-11-16

申请人： STMicroelectronics International N.V.

发明人： CURINA, Carlo ,  BENDOTTI, Valerio ,  DE CAMPO, Nicola ,  GENNARI SANTORI, Valerio

IPC分类号： H03K17/06 ,  H03K17/689

CPC分类号： H03K17/689 ,  H03K17/063 ,  H03K2217/006320130101

摘要： A receiver circuit (104') receives a differential signal (Vd) that includes positive and negative spikes, and produces an output signal (PWMRX) as a function of the differential signal. A first comparator (42) produces an intermediate set signal (COMPN) that includes a pulse at each positive spike of the differential signal, and a second comparator (44) produces an intermediate reset signal (COMPP) that includes a pulse at each negative spike of the differential signal. A logic circuit (90) detects whether the digital signal (PWMRX) switches between a first value and a second value, and whether the intermediate reset signal (COMPP) and the intermediate set signal (COMPN) include pulses lasting longer than a threshold. The logic (90) produces a set correction signal - respectively, a reset correction signal - that includes a pulse when the digital signal (PWMRX) switches and, at the same time, the intermediate reset signal - respectively, the intermediate set signal - includes a pulse lasting longer than the threshold. The logic (90) produces a corrected set signal (COMP'N) - respectively, a corrected reset signal (COMP'P) - that includes the pulses of the intermediate set signal (COMPN) - respectively, the pulses of the intermediate reset signal (COMPP) - and the pulses of the set correction signal- respectively, the pulses of the reset correction signal. An output circuit (46) asserts the output signal (PWMRX) in response to a pulse detected in the corrected set signal (COMP'N) and de-asserts the output signal (PWMRX) in response to a pulse detected in the corrected reset signal (COMP'P).

公开(公告)号：EP4383518A1

公开(公告)日：2024-06-12

申请号：EP23166043.2

申请日：2023-03-31

申请人： STMicroelectronics International N.V.

发明人： WUTTE, Rene

IPC分类号： H02J50/10 ,  H02J50/20 ,  H02J50/80 ,  H02J7/00

CPC分类号： H02J50/10 ,  H02J50/20 ,  H02J50/80 ,  H02J50/001 ,  H02J7/007 ,  H02J2207/1020200101

摘要： The present disclosure relates to a wireless electronics device comprising:
- an antenna (202) for receiving a radio frequency signal;
- an energy storage device for storing electrical energy;
- a frequency detection circuit configured to detect whether the received radio frequency signal is in a first frequency range or in a second frequency range, the first and second frequency ranges being non-overlapping;
- a first communications circuit configured to transmits a first return signal if the radio frequency signal is in the first frequency range and to establish wireless charging of the energy storage device according to a first protocol; and
- a second communications circuit configured to transmits a second return signal if the radio frequency signal is in the second frequency range and to establish wireless charging of the energy storage device according to a second protocol.

公开(公告)号：EP4362331A1

公开(公告)日：2024-05-01

申请号：EP23202746.6

申请日：2023-10-10

申请人： STMicroelectronics International N.V.

发明人： BIANCHI, Simone ,  POLETTO, Vanni

IPC分类号： H03F3/45 ,  G01R1/20 ,  G01R19/00 ,  H02J7/34

CPC分类号： H02J7/342 ,  G01R1/203 ,  G01R19/0092 ,  H03F2200/45320130101 ,  H03F2200/29720130101 ,  H03F2200/4520130101

摘要： A circuit (200') for use, e.g., as current sense amplifier in a DC-DC converter in a hybrid vehicle comprises:
a first input node (INP) and a second input node (INM), configured to have an input voltage signal (IHSEN, ILSEN) applied therebetween,
a floating-ground input stage (IS) configured to operate between a first supply voltage (VLOW+5V) and a second non-zero supply voltage (VLOW) and to convert into a current signal the input voltage signal applied between the first input node (INP) and the second input node (INM), and
an output stage (OS) configured to receive the current signal from the floating-ground input stage (IS) and to convert the current signal back to an output voltage signal (AMPoutP, AMPoutM) referred to ground (GND).
The output voltage referred to ground is a replica of the input voltage signal applied between the first input node (INP) and the second input node (INM).