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公开(公告)号：EP0057135A2
公开(公告)日：1982-08-04
申请号：EP82400107.7
申请日：1982-01-21
CPC分类号： H01L29/66143 , H01L21/70 , H01L21/84 , H01L29/04 , H01L29/872
摘要： A Schottky diode is fabricated according to the following steps: forming a layer of metal-silicide on an underlying dielectric layer, forming a polysilicon layer on the upper surface of the metal-silicide layer, forming a second dielectric layer on the upper surface of the polysilicon layer and patterning the second dielectric layer to create a contact window through the second dielectric layer to an exposed surface region of the polysilicon layer, and forming a metal contact to the exposed surface region.
摘要翻译： 根据以下步骤制造肖特基二极管：在下面的介电层上形成金属硅化物层，在金属硅化物层的上表面上形成多晶硅层，在第二电介质层的上表面上形成第二电介质层 多晶硅层并且图案化第二电介质层以形成通过第二电介质层的接触窗到多晶硅层的暴露表面区域，并且与暴露的表面区域形成金属接触。
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92.发明公开
公开(公告)号：EP0052566A2
公开(公告)日：1982-05-26
申请号：EP81401794.3
申请日：1981-11-13
发明人： Tickle, Andrew C.
IPC分类号： G11C17/00
CPC分类号： G11C16/3486 , G11C8/12 , G11C16/0408 , G11C16/08 , G11C16/16 , G11C16/3459 , G11C16/3468 , G11C2216/28
摘要： An electrically erasable programmable read-only memory (E 2 PROM) is provided which utilizes an inhibit voltage applied to unselected word lines during writing to prevent writing in unselected rows. In the preferred embodiment, each memory cell of the E 2 PROM array consists of a single floating gate field effect transistor. The E 2 PROM of the present invention provides for row erasure and single bit writing.
摘要翻译： 提供了一种电可擦除可编程只读存储器（E2PROM），其在写入期间利用施加到未选择字线的禁止电压以防止在未选择的行中写入。 在优选实施例中，E2PROM阵列的每个存储单元由单个浮栅场效应晶体管组成。 本发明的E2PROM提供行擦除和单位写入。
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公开(公告)号：EP0052048A2
公开(公告)日：1982-05-19
申请号：EP81401721.6
申请日：1981-10-28
发明人： Sloane, Edwin A.
IPC分类号： H03M1/10
CPC分类号： G06G7/19 , H03M1/1071
摘要： A method and apparatus is described for dynamically testing the overall performance characteristics of digital-to-analog converts and analog-todigital converters which involve excitation of the converters by an orthogonal function signal. Specifically the method comprises dynamically exercising a converter with an analog or digital signal pattern characterized by the sum of a set of mutually orthogonal functions, the sum having substantially uniform amplitude distribution among allowable states (maximum entropy), and simultaneously examining the output response of the converter for a plurality of basic performance parameters. The basic performance parameters typically include distortion, linearity and optimum gain. The simultaneous examination involves sorting out expected responses to simultaneously applied orthogonal signals. The method yields a relatively complete statistical description of the performance characteristics. The preferred excitation is based on the Walsh functions. The output response is readily analyzed by Fast Walsh Transform processors.
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公开(公告)号：EP0077736B1
公开(公告)日：1989-03-22
申请号：EP82401915.2
申请日：1982-10-19
发明人： Hughes, John J., Jr.
CPC分类号： G01R31/318371 , G01R31/31921
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95.发明授权Apparatus for dynamically controlling the timing of signals in automatic test systems 失效用于动态控制自动测试系统中信号时序的设备
公开(公告)号：EP0136203B1
公开(公告)日：1988-09-14
申请号：EP84401605.5
申请日：1984-08-01
CPC分类号： G01R31/31935 , G01R31/31713 , G01R31/3191 , G01R31/31922 , G01R31/31924 , G01R31/31926 , G01R31/31928 , G01R31/31937 , G11C7/22 , H03K5/131 , H03K5/14 , H03K2005/00247 , H03K2005/00254 , H03K2005/0026
摘要： A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators. Each of the three period generators includes two interconnected timing interval generators 30 and 40 that alternately generate overlapping timing signals. Each timing interval generator includes a stop-restart oscillator 32, a counter 34, and a delay-line vernier 36. Upon the receipt of a start signal, the oscillator stops and restarts to align its clock pulses to the start signal. The oscillator output clocks the counter, which supplies a signal to the vernier when a preselected number is reached. The vernier delays the counter signal by a preselected delay and issus a signal that designates the end of the period.
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公开(公告)号：EP0153889A3
公开(公告)日：1988-08-10
申请号：EP85400247
申请日：1985-02-14
发明人： Hsia, Yukun
CPC分类号： H01L21/31155 , H01L21/28211 , H01L21/28273 , H01L21/321 , H01L29/51
摘要： A process for improving the quality of an oxide thermally grown or doped polysilicon by doping the polysilicon so that the V I resistance of the polysilicon is less than approximately 3 ohms as measured by a companion single crystal test wafer The process applied to an EPROM device eliminates deprogramming defects in the device.
摘要翻译： 通过掺杂多晶硅来改善氧化物热生长或掺杂多晶硅的质量的方法，使得通过伴随的单晶测试晶片测量的多晶硅的VI电阻小于约3欧姆。应用于EPROM器件的工艺消除了去规划 设备缺陷。
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公开(公告)号：EP0136207B1
公开(公告)日：1988-03-30
申请号：EP84401610.5
申请日：1984-08-01
IPC分类号： G01R31/28
CPC分类号： G01R31/31935 , G01R31/31713 , G01R31/3191 , G01R31/31922 , G01R31/31924 , G01R31/31926 , G01R31/31928 , G01R31/31937 , G11C7/22 , H03K5/131 , H03K5/14 , H03K2005/00247 , H03K2005/00254 , H03K2005/0026
摘要： A timing subsystem 10 including several test period generators for supplying a variety of timing signals to a device under test. Major, minor, and free-run period generators each supply various timing signals to a multiplexer 18, which selectively connects the timing signals to timing generators 20. A central processing unit 28 supplies data to the period generators and timing generators to define their respective timing signals. Timing signals generated by the major period generator 12 define the overall testing rate. The minor period generator 14 generates multiple timing signals within the periods of the major clock signals to permit higher clock rates. Timing signals that are independent of the major clock periods are generated by the free-run period generator 16. An external synchronizer circuit 26 provides a feedback loop from the device under test 22 to the major period generator. A reference driver trigger delay circuit 27 provides means for calibrating the timing generators. Each of the three period generators includes two interconnected timing interval generators 30 and 40 that alternately generate overlapping timing signals. Each timing interval generator includes a stop-restart oscillator 32, a counter 34, and a delay-line vernier 36. Upon the receipt of a start signal, the oscillator stops and restarts to align its clock pulses to the start signal. The oscillator output clocks the counter, which supplies a signal to the vernier when a preselected number is reached. The vernier delays the counter signal by a preselected delay and issus a signal that designates the end of the period.
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公开(公告)号：EP0133117A3
公开(公告)日：1988-01-27
申请号：EP84401525
申请日：1984-07-19
发明人： Willis, Calvin E.
CPC分类号： G06F13/128 , G06F13/28 , H04L29/00
摘要： A data processing system (20) incorporates host processors (22 and 24) connected by network interface units (28 and 34) to a coaxial cable (26). The network interface units (28 and 34), cable (26), and network interface units (40-56) form a local area network capable of carrying out processing operations on information independent of the host processors (22 and 24). As a result, interrupts of the host processors (22 and 24) for data transfer operations are significantly reduced, allow- , ing the system (20) to support a much larger number of user terminals and other peripherals.
摘要翻译： 数据处理系统（20）包括通过网络接口单元（28和34）连接到同轴电缆（26）的主处理器（22和24）。 网络接口单元（28和34），电缆（26）和网络接口单元（40-56）形成能够对与主处理器（22和24）无关的信息执行处理操作的局域网。 结果，用于数据传输的主机处理器（22和24）的中断显着减少，允许系统（20）支持更大数量的用户终端和其他外围设备。
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公开(公告)号：EP0146452A3
公开(公告)日：1987-11-19
申请号：EP84402429
申请日：1984-11-28
CPC分类号： H01L24/85 , B23K20/007 , H01L24/45 , H01L24/78 , H01L2224/45015 , H01L2224/45124 , H01L2224/78 , H01L2224/8503 , H01L2224/85203 , H01L2224/85205 , H01L2924/00014 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/01057 , H01L2924/01082 , H01L2924/12041 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/20753 , H01L2924/3025 , H01L2224/48 , H01L2924/00015 , H01L2224/05599 , H01L2924/00
摘要： A method, timing control circuit, and power supply are described for initiating arc discharge between the cover gas delivery shroud and lead wire held in the bonding tool of a lead wire bonding machine for melting and forming a ball at the end of the lead wire. An arc discharge timing control pulse controls duration of the arc discharge within an empirically determined time window between the shortest and longest durations of arc discharge which result in optimal ball formation of a substantially spherical ball at the end of the lead wire without necking of the lead wire above the formed ball. The timing control circuit also provides an initial cover gas movement delay before ball formation for displacing oxygen from the shield and the end of the lead wire, and a subsequent cooling delay for solidifying and cooling the formed ball in the cover gas stream prior to ball bonding. Initially, the lead wire tail length extending below the bonding tool is selected to provide a ball of specified size; the voltage is selected according to tail length to form the mass of tail length metal into a substantially spherical ball; and a neck of desired thickness is selected by adjusting the duration of the arc discharge timing control pulse within the time window.
摘要翻译： 描述了一种方法，定时控制电路和电源，用于启动保护在引线接合机的接合工具中的覆盖气体输送护罩和引线之间的电弧放电，用于在引线的端部熔化和形成球。 电弧放电定时控制脉冲控制在电弧放电的最短和最长持续时间之间的经验确定的时间窗内的电弧放电的持续时间，这导致在导线末端处的基本上球形的球的最佳球形成，而导线的颈缩 线上形成的球。 定时控制电路还提供在球形成之前的初始覆盖气体移动延迟，用于从屏蔽件和引线的端部移位氧气，以及随后的冷却延迟，用于在球接合之前固化和冷却覆盖气体流中形成的球体 。 定时控制脉冲被施加到球焊机上，并且还耦合到相对高压电源电路的晶体管电子开关，用于当电子开关导通时通过对屏蔽和引线的电阻施加电弧放电电压。 在低电压定时控制电路和高压电源电路之间使用光耦合来电隔离两个电压电平。 电弧放电的持续时间被控制在电弧放电的最长和最短持续时间之间的关键时间窗内，这导致最佳的球形成。 最初，选择在焊接工具下方延伸的引线尾长度以提供特定尺寸的球; 根据尾部长度选择电压，将尾部长度金属的质量形成为大致球形的球; 并且通过在时间窗内调整电弧放电定时控制脉冲的持续时间来选择所需厚度的颈部。
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公开(公告)号：EP0100736A3
公开(公告)日：1987-05-20
申请号：EP83401591
申请日：1983-08-01
发明人： Milgram, Alvin
IPC分类号： H01L21/00
CPC分类号： G03F7/094 , H01L21/0272 , Y10S438/951
摘要： An improved lift-off process for forming metallized interconnections between various regions on a semiconductor device relies on the use of a particular polyimide in forming a protective mask over the device. The polyimide is a copolymer of an aromatic cycloaliphatic. diamine and a dianhydride which allows the resulting structure to withstand particularly high temperatures in the fabrication process. In particular, the polyimide when subjected to high temperature metallization under vacuum remains sufficiently soluble to be substantially completely removed from the device by immersion in common organic solvents. This allows high temperature metallization as interconnects for integrated circuits.
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