公开(公告)号：EP2244305A1

公开(公告)日：2010-10-27

申请号：EP09711133.0

申请日：2009-02-16

申请人： Unisantis Electronics (Japan) Ltd.

发明人： MASUOKA, Fujio ,  NAKAMURA, Hiroki ,  KUDO, Tomohiko ,  ARAI, Shintaro

IPC分类号： H01L29/786 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/42392 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78642

摘要： Disclosed is a semiconductor device production method, which comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer on a planar semiconductor layer; forming a second-conductive-type semiconductor layer in a portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a gate dielectric film and a gate electrode having a laminated structure of a metal film and an amorphous silicon or polysilicon film, around the pillar-shaped first-conductive-type semiconductor layer; forming a sidewall-shaped dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode; forming first and second sidewall-shaped dielectric films on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on the gate electrode; forming a contact on the second-conductive-type semiconductor layer formed in the portion of the planar semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; and forming a contact on the second-conductive-type semiconductor layer formed in the upper portion of the pillar-shaped first-conductive-type semiconductor layer.

摘要翻译： 公开了一种半导体器件制造方法，其包括以下步骤：在平面半导体层上形成柱状第一导电类型半导体层; 在所述柱状第一导电类型半导体层下方的所述平面半导体层的一部分中形成第二导电类型半导体层; 在所述柱状第一导电型半导体层周围形成具有金属膜和非晶硅或多晶硅膜的层叠结构的栅极电介质膜和栅电极; 在所述柱状的第一导电型半导体层的侧壁的上部区域形成侧壁状的电介质膜并与所述栅电极的上部接触的工序; 在栅电极的侧壁上形成第一和第二侧壁形状的介电膜; 在柱形第一导电类型半导体层的上部中形成第二导电类型半导体层; 在形成于柱状第一导电型半导体层下方的平面型半导体层的一部分中的第二导电型半导体层上形成金属半导体化合物; 在形成于柱状第一导电型半导体层的上部的第二导电型半导体层上形成金属半导体化合物; 在栅电极上形成金属 - 半导体化合物; 在柱状第一导电型半导体层下方的平面半导体层的一部分中形成的第二导电型半导体层上形成接触; 以及在柱状第一导电类型半导体层的上部中形成的第二导电类型半导体层上形成接触。

公开(公告)号：EP2244301A1

公开(公告)日：2010-10-27

申请号：EP09709791.9

申请日：2009-02-16

申请人： Unisantis Electronics (Japan) Ltd.

发明人： MASUOKA, Fujio ,  KUDO, Tomohiko ,  ARAI, Shintaro ,  NAKAMURA, Hiroki

IPC分类号： H01L29/786 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/78642 ,  H01L29/42392

摘要： It is intended to provide an SGT production method capable of obtaining a structure for reducing a resistance of a source, drain and gate, a desired gate length, desired source and drain configurations and a desired diameter of a pillar-shaped semiconductor to be obtained. The method comprises the steps of: forming a pillar-shaped first-conductive-type semiconductor layer; forming a second-conductive-type semiconductor layer underneath the pillar-shaped first-conductive-type semiconductor layer; forming a dummy gate dielectric film and a dummy gate electrode around the pillar-shaped first-conductive-type semiconductor layer; forming a first dielectric film on an upper region of a sidewall of the pillar-shaped first-conductive-type semiconductor layer and in contact with a top of the gate electrode, through a gate dielectric film; forming a first dielectric film on a sidewall of the gate electrode; forming a second-conductive-type semiconductor layer in an upper portion of the pillar-shaped first-conductive-type semiconductor layer; forming a metal-semiconductor compound on each of the second-conductive-type semiconductor layers formed in the upper portion of and underneath the pillar-shaped first-conductive-type semiconductor layer; removing the dummy gate dielectric film and the dummy gate electrode and forming a high-k gate dielectric film and a metal gate electrode.

摘要翻译： 旨在提供一种SGT制造方法，其能够获得用于减小要获得的柱状半导体的源极，漏极和栅极的电阻，期望的栅极长度，期望的源极和漏极配置以及期望的直径的结构。 该方法包括以下步骤：形成柱状的第一导电型半导体层; 在柱形第一导电类型半导体层下方形成第二导电类型半导体层; 在所述柱状第一导电型半导体层周围形成伪栅极电介质膜和伪栅电极; 通过栅极介电膜在柱状第一导电型半导体层的侧壁的上部区域上形成第一介电膜并且与栅极的顶部接触; 在栅电极的侧壁上形成第一介电膜; 在柱形第一导电类型半导体层的上部中形成第二导电类型半导体层; 在形成于所述柱状第一导电型半导体层的上部和下部的每个所述第二导电型半导体层上形成金属半导体化合物; 去除伪栅介质膜和伪栅电极，并形成高k栅介质膜和金属栅电极。

公开(公告)号：EP2232561A1

公开(公告)日：2010-09-29

申请号：EP08857769.7

申请日：2008-11-21

申请人： Semiconductor Energy Laboratory Co, Ltd.

发明人： MIYAIRI, Hidekazu ,  KOMORI, Shigeki ,  ISA, Toshiyuki ,  KOMATSU, Ryu

IPC分类号： H01L29/786 ,  G09F9/30 ,  H01L21/336 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78609

摘要： A manufacturing method of a thin film transistor and a display device using a small number of masks is provided. A first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked. Then, a resist mask having a recessed portion is formed thereover using a multi-tone mask. First etching is performed to form a thin-film stack body, and second etching in which the thin-film stack body is side-etched is performed to form a gate electrode layer. The resist is made to recede, and then, a source electrode, a drain electrode, and the like are formed; accordingly, a thin film transistor is manufactured.

公开(公告)号：EP1842240B1

公开(公告)日：2010-07-21

申请号：EP05826022.5

申请日：2005-12-02

申请人： International Business Machines Corporation

发明人： CALLEGARI, Alessandro C. ,  GRIBELYUK, Michael A. ,  LACEY, Dianne L. ,  MCFEELY, Fenton R. ,  SAENGER, Katherine L. ,  ZAFAR, Sufi

IPC分类号： H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  C23C14/06 ,  C23C14/34

CPC分类号： H01L29/4966 ,  C23C14/0036 ,  C23C14/0635 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

公开(公告)号：EP1456888B1

公开(公告)日：2010-07-21

申请号：EP02794406.5

申请日：2002-12-19

申请人： GlobalFoundries, Inc.

发明人： BULLER, James, F. ,  XIANG, Qi ,  WRISTERS, Derick, J.

IPC分类号： H01L29/49 ,  H01L29/78 ,  H01L29/423 ,  H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/42376 ,  H01L29/66484 ,  H01L29/6656

摘要： High-speed MOS transistors (32) are provided by forming a conductive layer (24) embedded in transistor gate sidewall spacers (27). The embedded conductive layer (24) is electrically insulated from the gate electrode (18) and the source/drain regions (28) of the transistor (32). The embedded conductive layer (24) is positioned over the source/drain extensions (30) and causes charge to accumulate in the source/drain extensions (30) lowering the series resistance of the source/drain regions (28).

公开(公告)号：EP1946379B1

公开(公告)日：2010-06-02

申请号：EP06836832.3

申请日：2006-11-02

申请人： ADVANCED MICRO DEVICES, INC.

发明人： PAN, James ,  PELLERIN, John

IPC分类号： H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L21/336

CPC分类号： H01L21/28008 ,  H01L21/28088 ,  H01L21/28238 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

公开(公告)号：EP2112687A2

公开(公告)日：2009-10-28

申请号：EP08075619.0

申请日：2008-07-11

申请人： IMEC ,  Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chang, Shou-zen ,  Yu, Hong Yu

IPC分类号： H01L21/8238 ,  H01L29/51 ,  H01L29/49

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A dual workfunction semiconductor device comprising a first gate stack and a second gate stack, having different workfunctions; wherein the first gate stack comprises a second metal electrode overlying a second dielectric capping layer, overlying a barrier metal electrode, the barrier metal electrode overlying a first metal electrode layer, overlying the dielectric host layer, the dielectric host layer overlying a first dielectric capping layer, overlying the semiconductor substrate in the first region and wherein the second gate stack comprises a second metal electrode overlying a second dielectric capping layer, overlying the first metal electrode, the first metal electrode overlying the dielectric host layer, overlying the semiconductor substrate in the second region and wherein the second metal electrode layer consists of the same metal composition as the first metal electrode layer. Also a method for forming a dual workfunction device is disclosed.

摘要翻译： 一种双功函数半导体装置，包括一第一栅极堆叠和第二栅极堆叠，具有不同功函数; worin第一栅极堆叠包括第二金属电极覆盖的第二介电顶盖层，上覆的阻挡金属电极，所述阻挡金属电极覆盖在第一金属电极层，覆盖在所述介电基质层，所述介电基质层，覆盖第一介电顶盖层 ，在所述第一区域覆盖所述半导体基板和worin第二栅堆叠包括第二金属电极覆盖的第二介电顶盖层，覆盖所述第一金属电极，所述第一金属电极覆盖在所述介电基质层，在所述第二覆盖所述半导体基片 区域和worin相同的金属组成与第一金属电极层的第二金属电极层besteht。 也可用于形成双功函数装置的制造方法是游离缺失盘。

公开(公告)号：EP1977446A4

公开(公告)日：2009-09-23

申请号：EP07710062

申请日：2007-01-11

申请人： IBM

发明人： ANDERSON BRENT A ,  CHAN VICTOR W C ,  NOWAK EDWARD J

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/76 ,  H01L29/423 ,  H01L29/49

CPC分类号： H01L29/66477 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28518 ,  H01L29/1083 ,  H01L29/42376 ,  H01L29/66507 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

公开(公告)号：EP2101346A1

公开(公告)日：2009-09-16

申请号：EP07860159.8

申请日：2007-12-26

申请人： ULVAC, INC.

发明人： TAKASAWA, Satoru ,  TAKEI, Masaki ,  TAKAHASHI, Hirohisa ,  KATAGIRI, Hiroaki ,  UKISHIMA, Sadayuki ,  TANI, Noriaki ,  ISHIBASHI, Satoru ,  MASUDA, Tadashi

IPC分类号： H01L21/3205 ,  G02F1/1343 ,  G02F1/1368 ,  H01L21/285 ,  H01L21/336 ,  H01L23/52 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L23/53238 ,  H01L21/2855 ,  H01L27/124 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/16 ,  H05K3/388 ,  H01L2924/00

摘要： A wiring film having excellent adhesion and a low resistance is formed. A barrier film 22 having copper as a main component and containing oxygen is formed on an object 21 to form a film thereon by introducing an oxygen gas into a vacuum chamber 2 in which the object 21 to form a film thereon and sputtering a pure copper target 11. Then, after the introduction of the oxygen gas is stopped, a low-resistance film 23 made of pure copper is formed by sputtering the pure copper target 11. Since the barrier film 22 and the low-resistance film 23 have copper as the main component, they can be patterned at a time. Since the low-resistance film 23 has a resistance lower than that of the barrier film 22, the resistance of the whole wiring film 25 is reduced. Since the barrier layer 22 has high adhesion to glass and silicon, the whole wiring film 25 has high adhesion.

摘要翻译： 形成具有优异的粘附性和低电阻的布线膜。 在物体21上形成具有铜作为主要成分并含有氧的阻挡膜22，以在其上通过将氧气引入到其中物体21以在其上形成膜的真空室2中并溅射纯铜靶 然后，在停止引入氧气之后，通过溅射纯铜靶11来形成由纯铜制成的低电阻膜23.由于阻挡膜22和低电阻膜23具有铜作为 主要组件，它们可以一次被图案化。 由于低电阻膜23的电阻低于阻挡膜22的电阻，因此整个布线膜25的电阻降低。 由于阻挡层22对玻璃和硅具有高粘附性，所以整个布线膜25具有高粘附性。

公开(公告)号：EP2096676A1

公开(公告)日：2009-09-02

申请号：EP09153744.9

申请日：2009-02-26

申请人： Commissariat à l'Energie Atomique

发明人： Bernard, Emilie ,  Guillaumot, Bernard ,  Coronel, Philippe ,  Vizioz, Christian

IPC分类号： H01L29/49 ,  H01L29/786

CPC分类号： H01L29/4908 ,  H01L29/42392 ,  H01L29/66787 ,  H01L29/78696

摘要： L'invention concerne un procédé de fabrication d'un dispositif semi-conducteur comportant une région semi-conductrice de canal et une région de grille, la région de grille comprenant au moins une partie enterrée s'étendant sous la région de canal. La formation de la partie enterrée de la région de grille comprend :
- une formation d'une cavité sous la région de canal,
- le remplissage de la cavité par un premier matériau,
- la mise en contact avec le premier matériau, d'aluminium ou d'un deuxième matériau semi-conducteur différent du premier,
- une substitution du premier matériau par l'aluminium, ou la diffusion du second matériau semi-conducteur dans le premier matériau.

摘要翻译： 该方法包括形成腔体即 中空空间，下方的半导体沟道区，以及填充所述空腔由材料，例如 锗多晶硅。 铝或半导体材料与前者材料接触。 前者材料由铝代替，或第三材料由前材料中的半导体材料的扩散而形成。 腔室形成，接触和更换阶段，成型阶段第三材料执行用于形成栅极区，其中，该经埋藏部分包括的材料的铝或铝合金的掩埋部分。 因此独立claimsoft被包括为一个半导体器件，包括一个信道半导电区域。