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    PSEUDO DUAL PORT MEMORY USING A DUAL PORT CELL AND A SINGLE PORT CELL WITH ASSOCIATED VALID DATA BITS AND RELATED METHODS
    101.
    发明公开
    PSEUDO DUAL PORT MEMORY USING A DUAL PORT CELL AND A SINGLE PORT CELL WITH ASSOCIATED VALID DATA BITS AND RELATED METHODS 有权
    具有双重PORT-CELL伪双端口存储器，并与相关有效数据位和相关程序的单一端口-CELL

    公开(公告)号：EP3038109A1

    公开(公告)日：2016-06-29

    申请号：EP15187696.8

    申请日：2015-09-30

    申请人： STMicroelectronics International N.V.

    发明人： Rawat, Harsh ,  JAIN, PIYUSH

    IPC分类号： G11C8/16 ,  G11C7/10 ,  G11C11/419 ,  G11C11/418

    CPC分类号： G11C11/419 ,  G11C7/1045 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/418

    摘要： A pseudo dual port memory includes a set of dual port memory cells having a read port and a write port, and configured to store data words in each of a plurality of addressed locations, and a set of single port memory cells having a read/write port, and configured to store data words in each of a plurality of addressed locations. A valid data storage unit is configured to store valid bits corresponding to the addressed locations of the set of dual port memory cells and the set of single port memory cells. Control circuitry is configured to access the addressed locations of the set of dual port memory cells and the set of single port memory cells. The control circuitry performs a simultaneous write operation using the write port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and updates corresponding valid bits in the valid data storage unit, and performs a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single port memory cells, using the read port of the set of dual port memory cells and the read/write port of the set of single port memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage unit.

    摘要翻译： 伪双端口存储器包括一组具有一个读端口和一个写端口的双端口存储器单元，并且在每个寻址位置的多个被配置为存储数据字，并具有读一组单端口存储器单元的/写 端口，和被配置为存储在每个寻址位置的多个数据字。 一个有效的数据存储单元被配置为存储有效位对应给组双端口存储器单元和所述一组单端口存储器单元的位置。 控制电路被配置成访问所述组双端口存储器单元和所述一组单端口存储器单元的被寻址的位置。 所述控制电路使用所述一组双端口存储器单元和所述一组单端口存储器单元的读/写端口的写端口执行同时写入操作，而在有效数据存储单元对应的有效比特的更新，并执行 并行读出手术，在所述一组双端口存储器单元和所述一组单端口存储器单元中的一个相同的寻址位置，使用所设置的双端口存储器单元的读取端口和该组单个端口的读/写端口 存储单元，和确定性采矿哪个存储的数据字是有效的基于所述的有效数据存储单元中的对应的有效比特。

    Integrated circuit for storing data
    102.
    发明公开
    Integrated circuit for storing data 审中-公开
    Integrierte Schaltung zur Speicherung von Daten

    公开(公告)号：EP2988305A1

    公开(公告)日：2016-02-24

    申请号：EP14181308.9

    申请日：2014-08-18

    申请人： Synopsys, Inc.

    发明人： Siddiqui, Mohammed Sultan Mohiuddin ,  Sharad, Shailendra ,  Khanuja, Amit ,  Vats, Hemant

    IPC分类号： G11C11/419 ,  G11C7/22 ,  G11C8/08 ,  G11C11/418

    摘要： An integrated circuit (10) for storing data comprises a memory cell array (100) comprising a plurality of bit cells (BC1, ..., BCn) comprising a first and a second one of the bit cells (BC1, BC2) having a static random access memory architecture. The first and the second bit cells (BC1, BC2) are coupled to a common wordline (WL_TOP) and are arranged in different columns (C1, C2) of the memory cell array (100). During a write access to the first bit cell (BC1), the first bit cell (BC1) undergoes a write operation, whereas the second bit cell (BC2) is a half-selected bit cell which undergoes a pseudo read operation. The integrated circuit (10) uses a two-phase write scheme to improve the write-ability in low operating voltage environment.

    摘要翻译： 一种用于存储数据的集成电路（10）包括包括多个比特单元（BC1，...，BCn）的存储单元阵列（100），包括第一和第二位单元（BC1，BC2） 静态随机存取存储器架构。 第一和第二位单元（BC1，BC2）耦合到公共字线（WL_TOP），并且被布置在存储单元阵列（100）的不同列（C1，C2）中。 在对第一位单元（BC1）的写访问期间，第一位单元（BC1）进行写操作，而第二位单元（BC2）是经历伪读操作的半选位单元。 集成电路（10）使用两相写入方案来提高低工作电压环境下的写入能力。

    CLOCK AND CONTROL SIGNAL GENERATION FOR HIGH PERFORMANCE MEMORY DEVICES
    105.
    发明公开
    CLOCK AND CONTROL SIGNAL GENERATION FOR HIGH PERFORMANCE MEMORY DEVICES 审中-公开
    时钟和控制信号生成用于高性能存储设备

    公开(公告)号：EP2158592A1

    公开(公告)日：2010-03-03

    申请号：EP08769948.4

    申请日：2008-05-31

    申请人： QUALCOMM Incorporated

    发明人： CHEN, Zhiqin ,  JUNG, Chang Ho

    IPC分类号： G11C11/418 ,  G11C11/419 ,  G11C7/22

    CPC分类号： G11C11/418 ,  G11C7/222 ,  G11C7/227 ,  G11C11/419 ,  G11C2207/2281 ,  G11C2207/229

    摘要： Techniques for generating clock and control signals to achieve good performance for read and write operations in memory devices are described. In one design, a clock and control signal generator within a memory device includes first and second clock generators, first and second control signal generators, and a reset circuit. The first clock generator generates a first clock signal used for read and write operations. The second clock generator generates a second clock signal used for write operations. The reset circuit generates at least one reset signal for the first and second clock generators. The reset signal(s) may have timing determined based on loading due to dummy cells. The first control signal generator generates control signals used for read and write operations based on the first clock signal. The second control signal generator generates control signals used for write operations based on the second clock signal.

    RANDOM-ACCESS MEMORY DEVICES COMPRISING A DIODED BUFFER
    106.
    发明授权
    RANDOM-ACCESS MEMORY DEVICES COMPRISING A DIODED BUFFER 有权
    带缓冲二极管直接访问存储器安排

    公开(公告)号：EP1417686B1

    公开(公告)日：2008-01-02

    申请号：EP02760452.9

    申请日：2002-08-07

    申请人： NXP B.V.

    发明人： STOJANOV, Nikola

    IPC分类号： G11C11/418 ,  G11C8/08

    CPC分类号： G11C8/08

    摘要： Random-access memory device (20) comprising select lines (27; 47), bit lines (21.1 - 21.3), and several RAM cells (22.1 - 22.3), each RAM cell (22.1 - 22.3) being connected to a corresponding one of said select lines (27; 47)and to a corresponding one of said bit lines (21.1 - 21.3). The random-access memory device (20) further comprises select buffers (26; 46) for selecting the read-out of one out of the select lines (27; 47) when receiving a selection signal. Each of the select buffers (26; 46) comprises an inverter (29) serving as driver. The inverter (29) is being followed by a diode (30) for limiting output voltage swings at the respective select line (27; 47).

    Semiconductor memory device
    109.
    发明公开
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：EP1278198A2

    公开(公告)日：2003-01-22

    申请号：EP02254461.3

    申请日：2002-06-26

    申请人： SHARP KABUSHIKI KAISHA

    发明人： Kamiyama, Koichi

    IPC分类号： G11C8/06 ,  G11C11/418

    CPC分类号： G11C8/10 ,  G11C7/12 ,  G11C8/18

    摘要： A semiconductor memory device includes a memory cell provided at each of intersections of word lines and bit lines and connected to the corresponding word line and the corresponding bit line; an address transition detection circuit; an address latch circuit; an address decoder; a pre-charging circuit; and a control signal generation circuit. The address latch circuit is controlled by a bit line pre-charging signal, such that while the bit line pre-charging signal is at a first logic level, the address signal is input to the address latch circuit, and while the bit line pre-charging signal is at a second logic level, the input address signal is maintained by the address latch circuit. The address decoder is activated by the decoder activating signal. The address decoder is activated, the word line corresponding to the address signal is activated, and the memory cell connected to the corresponding word line is accessed.

    摘要翻译： 一种半导体存储器件，包括：存储单元，设置在字线和位线的每个交叉处并连接到对应的字线和对应的位线; 地址转换检测电路; 地址锁存电路; 地址解码器; 预充电电路; 和控制信号生成电路。 地址锁存电路由位线预充电信号控制，使得当位线预充电信号处于第一逻辑电平时，地址信号被输入到地址锁存电路，并且当位线预充电信号被输入到地址锁存电路时， 充电信号处于第二逻辑电平，输入地址信号由地址锁存电路维持。 地址解码器由解码器激活信号激活。 地址解码器被激活，对应于地址信号的字线被激活，并且连接到相应字线的存储单元被访问。

    A synthesizable synchronous static RAM
    110.
    发明公开
    A synthesizable synchronous static RAM 审中-公开
    Synthesierbarer同步静态RAM内存

    公开(公告)号：EP1209687A3

    公开(公告)日：2002-09-18

    申请号：EP01127859.5

    申请日：2001-11-22

    申请人： STMicroelectronics Ltd.

    发明人： Dubey, Prashant

    IPC分类号： G11C11/41 ,  G11C11/418 ,  G11C11/419 ,  G06F17/50

    CPC分类号： G11C11/418 ,  G11C11/41 ,  G11C11/419

    摘要： This invention relates to a synthesizable, synchronous static RAM comprising custom built memcells and a semi-custom IO / precharge section in form of bit slice, a semi-custom built decoder connected to said bit slice and a semi-custom built control clock generation section, which is connected to said semi-custom built decoder and IO section. The arrangement being such as to provides high speed access, easy testability and asynchronous initialization capabilities while reducing design time in a size that is significantly smaller than existing semi custom or standard cell base memory design.