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    ASIC CLOCK FLOOR PLANNING METHOD AND STRUCTURE
    151.
    发明公开
    ASIC CLOCK FLOOR PLANNING METHOD AND STRUCTURE 审中-公开
    方法与结构ASIC的行程限制计划

    公开(公告)号：EP1584050A4

    公开(公告)日：2008-06-04

    申请号：EP02792424

    申请日：2002-12-17

    Applicant: IBM

    Inventor： ARTHANARI GEETHA ,  CARRIG KEITH M ,  LASHER MARK R ,  MENARD DANIEL R

    IPC: G06F1/04 ,  G06F17/50

    CPC classification number: G06F1/10 ,  G06F17/5072 ,  G06F2217/62

    Abstract: A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks (110); positioning a temporary reference insertion point (TIP) (120); grouping the sinks together with structured clock buffers (SCBs) in a set of levels (140); and moving the SCBs to improve symmetry of the tree (150). The SCBs may be of several sizes and may be positioned horizontally (42) or vertically (45) and moved within limits (46) to permit the program to calculate a complete tree.

    ISSUANCE AND EXECUTION OF MEMORY INSTRUCTIONS TO AVOID READ-AFTER-WRITE HAZARDS
    153.
    发明公开
    ISSUANCE AND EXECUTION OF MEMORY INSTRUCTIONS TO AVOID READ-AFTER-WRITE HAZARDS 审中-公开
    发行及存储器的指令的执行，以防止读到写危害

    公开(公告)号：EP1388053A4

    公开(公告)日：2008-04-16

    申请号：EP01987447

    申请日：2001-12-21

    Applicant: IBM

    Inventor： BILARDI GIANFRANCO ,  PATTNAIK PRATAP CHANDRA ,  EKANADHAM KATTAMURI

    IPC: G06F9/312 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38

    CPC classification number: G06F9/30043 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3885

    Abstract: A method and apparatus for issuing and executing memory instructions so as to maximize the number of requests issued to a highly pipelined memory and avoid reading data from memory (10) before a corresponding write to memory (10). The memory is divided into a number of regions, each of which is associated with a fence counter (18) that is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions (23) are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

    REDUCTION OF BORON DIFFUSIVITY IN pFETs
    154.
    发明公开
    REDUCTION OF BORON DIFFUSIVITY IN pFETs 审中-公开
    VERRINGERUNG DERBORDIFFUSIVITÄT在PFETS

    公开(公告)号：EP1692717A4

    公开(公告)日：2008-04-09

    申请号：EP03819249

    申请日：2003-12-08

    Applicant: IBM

    Inventor： BUEHRER FREDERICK WILLIAM ,  CHIDAMBARRAO DURESETI ,  DORIS BRUCE B ,  HUANG HSIANG-JEN ,  YANG HAINING

    IPC: H01L21/336 ,  H01L21/22 ,  H01L21/265 ,  H01L21/324 ,  H01L21/425 ,  H01L21/8238 ,  H01L27/01 ,  H01L29/10 ,  H01L29/167 ,  H01L29/76

    CPC classification number: H01L29/7842 ,  H01L21/22 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

    Abstract: A stressed film applied across a boundary defined by a structure or a body (e.g. substrate or layer ) of semiconductor material provides a change from tensile to compressive stress in the semiconductor material proximate to the boundary and is used to modify boron diffusion rate during annealing and thus modify final boron concentrations and/or profiles/gradients. In the case of a field effect transistor, the gate structure may be formed with or without sidewalls to regulate the location of the boundary relative to source/drain, extension and/or halo implants. Different boron diffusion rates can be produced in the lateral and vertical directions and diffusion rates comparable to arsenic can be achieved. Reduction of junction capacitance of both nFETs and pFETs can be achieved simultaneously with the same process steps.

    Abstract translation: 施加在由半导体材料的结构或主体（例如衬底或层）限定的边界上的应力膜提供了在接近边界的半导体材料中从拉应力至压应力的变化，并且用于修改退火期间的硼扩散速率和 从而改变最终的硼浓度和/或分布/梯度。 在场效应晶体管的情况下，栅极结构可以形成为具有或不具有侧壁以相对于源极/漏极，延伸和/或晕圈注入来调节边界的位置。 可以在横向和垂直方向上产生不同的硼扩散速率，并且可以实现与砷相当的扩散速率。 可以通过相同的工艺步骤同时实现nFET和pFET的结电容的降低。

    METHOD AND APPARATUS FOR PUBLISHING AND MONITORING ENTITIES PROVIDING SERVICES IN A DISTRIBUTED DATA PROCESSING SYSTEM
    155.
    发明公开
    METHOD AND APPARATUS FOR PUBLISHING AND MONITORING ENTITIES PROVIDING SERVICES IN A DISTRIBUTED DATA PROCESSING SYSTEM 审中-公开
    出版和监测ENTITûTEN的方法和装置，在分布式数据处理系统中的劳务提供

    公开(公告)号：EP1540500A4

    公开(公告)日：2008-03-26

    申请号：EP03749651

    申请日：2003-09-12

    Applicant: IBM

    Inventor： CHESS DAVID ,  SNIBLE EDWARD ,  WHALLEY IAN

    IPC: H04L29/06 ,  H04L29/08 ,  G06F15/173

    CPC classification number: H04L67/26 ,  H04L29/06 ,  H04L67/10 ,  H04L69/329

    Abstract: A method, apparatus, and computer instructions for providing identification and monitoring of entities. A distributed data processing system (100) includes one or more distributed publishing entities (400, 402, 404), which publish computer readable announcements (800) in a standard language. These announcements (800) may contain a description of a monitoring method (802) that may be used to monitor the behavior of one or more distributed monitored entities (400, 402, 404). These announcements also may include information used to identify a monitoring method (802) that may be used by the distributed monitored entity (400) to monitor its own behavior or by a distributed consumer entity to monitor the behavior of the distributed monitored entity (400). The monitoring also may be performed by a third-party distributed monitoring entity (400).

    HOT SWITCHABLE VOLTAGE BUS FOR IDDQ CURRENT MEASUREMENTS
    159.
    发明公开
    HOT SWITCHABLE VOLTAGE BUS FOR IDDQ CURRENT MEASUREMENTS 有权
    HOT可逆电压总线IDDQ电流测量

    公开(公告)号：EP1685417A4

    公开(公告)日：2008-01-16

    申请号：EP03768630

    申请日：2003-11-05

    Applicant: IBM

    Inventor： PASTEL LEAH M P

    IPC: G01R31/30 ,  G01R31/26

    CPC classification number: G01R31/3008

    Abstract: A voltage island system including a hot-switchable voltage bus for IDDQ current measurements. The voltage island system includes a plurality of voltage islands (V1, V2, ..., Vn), a global power system (102), and a quiescent power system (104). The global power system (102) includes a plurality of on-chip global header devices (H1, H2, ..., Hn) for selectively providing a voltage VDDg to the plurality of voltage islands in response to global header control signals (xl, x2, ..., xn), respectively. A global VDDg power supply (106) provides power to the global header devices (H1, H2, ..., Hn) via a VDDg power distribution grid/bus (108). The quiescent power system (104) includes a plurality of on-chip quiescent header devices (Hlq, H2q, ..., Hnq) for selectively providing a quiescent voltage VDDq to the plurality of voltage islands in response to quiescent header control signals xlq, x2q, ..., xnq, respectively. A quiescent VDDq power supply (110) provides power to the quiescent header devices via a VDDq power distribution grid/bus (112).

    SYSTEM AND METHOD FOR ELECTRONIC CHECK CONVERSION AT A POINT-OF-SALE TERMINAL
    160.
    发明公开
    SYSTEM AND METHOD FOR ELECTRONIC CHECK CONVERSION AT A POINT-OF-SALE TERMINAL 审中-公开
    系统和方法用于电子支票实现在销售点终端

    公开(公告)号：EP1476822A4

    公开(公告)日：2008-01-16

    申请号：EP02741963

    申请日：2002-05-20

    Applicant: IBM

    Inventor： HAYES JEFFERY ALAN ,  GEORGE JOHN L ,  RAEZER MARK EVANS

    IPC: G07D9/00 ,  G06K7/00 ,  G06Q20/04 ,  G06Q20/10 ,  G06Q20/20 ,  G07G1/00 ,  G07G1/06 ,  G07G1/12 ,  G06F17/00 ,  G06F17/60 ,  G06K5/00

    CPC classification number: G06Q20/04 ,  G06Q20/042 ,  G06Q20/108 ,  G06Q20/20 ,  G07G1/12

    Abstract: A system and method of electronic check processing at an existing point-of-sale (POS) system (10). A customer presents a check to pay for a transaction at the POS. A checker runs the check through an MICR scanner (22) and captures the MICR information from the check. The MICR information is forwarded to a verification system (12) for approval. Once the check is approved, the purchaser's contact information is scanned and digitized from the face of the check by an optical scanner (23) to create an ECC Agreement slip (150), which is printed on a high speed printer (24). Once the purchaser signs the agreement slip (150), he returns the slip (150) to the checker. The slip (150) is retained by the retailer and handled for cash balancing similarly to a charge card slip. The point-of-sale terminal (10) automatically voids the negotiable instrument (162) prior to the instrument (162) being returned to the purchaser to complete the transaction.

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