公开(公告)号：EP0210277B1

公开(公告)日：1993-03-31

申请号：EP86900844.1

申请日：1986-01-22

Applicant: SONY CORPORATION

Inventor： WATANABE, Nobuhisa

IPC: G06F11/00 ,  G06F1/00

CPC classification number: G06F1/22

Abstract: A memory device comprising a package (10) which has a plurality of terminals (12), at predetermined positions for inspecting program, and switching means (30) which is arranged in the package (10) and which switches the first and second operations. In the first operation, a rewritable read-only memory is connected to the terminals for inspecting program. In the second operation, inspection means (8) is connected to the terminals for inspecting program. In the first operation of the piggyback type, a rewritable ROM (EPROM) is connected to the terminals for program inspection of the package. In the second operation of the evaluator type, inspection means is connected to the terminals for program inspection of the package and is used as switching means, so that the operation can be automatically switched by a multiplication select circuit. Therefore the signal lines can be multiplexed to a great extent, and the piggyback-type chip and the evaluator-type chip can be used as the same device. Further, the same package can be used to accommodate the chips. This eliminates the need of separately developing the piggyback-type chip and the evaluator-type chip, and to separately produce the packages, contributing to shorten the time for developement and to reduce the cost of developement. Moreover, the piggyback-type chip, the evaluator-type chip and the mask ROM mounted chip can be made of the same pin arrangements. Therefore, the program can be evaluated by the evaluator-type chip with the mask ROM mounting board which is a final product, without requiring the traditionally employed interface substrate or the like.

公开(公告)号：EP0506060A1

公开(公告)日：1992-09-30

申请号：EP92105245.2

申请日：1992-03-27

Applicant: Hughes Aircraft Company

Inventor： Keech, Kimberly W. ,  Rothus, Robert J.

IPC: G06F13/40 ,  H03K19/0175

CPC classification number: G06F1/22 ,  G06F13/4072

Abstract: A current driver (10) is disclosed that includes an array of current buffers (80) and a program control circuit (12). The program control circuit (12) responds to an externally generated programming signal to generate buffer direction control, daisy chain configuration control, and tristate control signals. The buffers of the array of current buffers (80) are individually programmed by the direction control and the daisy chain configuration control signals to transmit data in one of a forward and reverse direction and to daisy chain a buffer (80) to a preceding buffer (80), respectively. The array of current buffers (80) is responsive to the tristate control signal to operate in a tristate mode. The array of current buffers (80) may be reprogrammed in response to a reset signal.

Abstract translation: 公开了包括当前缓冲器（80）和程序控制电路（12）的阵列的电流驱动器（10）。 程序控制电路（12）响应于外部产生的编程信号，以产生缓冲器方向控制，菊花链配置控制和三态控制信号。 电流缓冲器阵列（80）的缓冲器通过方向控制和菊花链配置控制信号被分别编程，以在正向和反向之一中发送数据，并将缓冲器（80）菊花链链接到前一缓冲器 80）。 电流缓冲器（80）的阵列响应三态控制信号以三态模式工作。 可以响应于复位信号对当前缓冲器（80）的阵列进行重新编程。

公开(公告)号：EP4413442A1

公开(公告)日：2024-08-14

申请号：EP22755001.9

申请日：2022-07-26

Applicant: Microsoft Technology Licensing, LLC

Inventor： ROYZEN, Evgeny

IPC: G06F1/22

CPC classification number: G06F1/0321 ,  G06F1/22

公开(公告)号：EP1722289A3

公开(公告)日：2015-07-22

申请号：EP06002790.1

申请日：2006-02-11

Applicant: 02Micro, Inc.

Inventor： Wong, Footshen ,  Popescu, Vlad ,  Han, Mingkwang ,  Wong, Winson ,  Lin, Chin Hsi

IPC: G06F1/22 ,  G06F1/26 ,  G06F1/30 ,  H03K19/173 ,  G06F1/32

CPC classification number: G06F1/26 ,  G06F1/22 ,  G06F1/30 ,  G06F1/32 ,  H03K19/1732

Abstract: A method for using a single pin to support both power input and power control functions for an integrated circuit, wherein the integrated circuit is in communication with a system. The method includes receiving at the pin a power input signal from the system, generating a power control signal based on the power input signal through a control signal generating circuit, and sending the power control signal to the integrated circuit.

公开(公告)号：EP1870794A3

公开(公告)日：2009-07-15

申请号：EP07012096.9

申请日：2007-06-20

Applicant: DENSO CORPORATION

Inventor： Kobayashi, Toshimasa c/o Denso Corporation

IPC: G06F1/24 ,  G06F1/32 ,  G06F1/22

CPC classification number: G06F1/24 ,  G06F1/22 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F11/0757 ,  Y02D10/126 ,  Y02D10/128

Abstract: In a microcomputer for executing at least one task in normal operation mode, a reset pin is provided. The microcomputer is configured to be reset upon a reset signal with an active level being inputted to the reset pin. A first clock generator is configured to generate a first clock with a first frequency. The microcomputer operates on the first clock as its operation clock. A disabling unit is electrically connected to the reset pin and configured to, upon the reset signal with the active level being input to the reset pin, disable the first clock generator.

公开(公告)号：EP1139108B1

公开(公告)日：2006-03-22

申请号：EP01200790.2

申请日：2001-03-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Swoboda, Gary L.

IPC: G01R31/3185

CPC classification number: G06F11/261 ,  G01R31/31705 ,  G01R31/318505 ,  G06F1/22 ,  G06F11/2733 ,  G06F11/3466

Abstract: An emulation controller (12) connected at a pin boundary of an integrated circuit (14) can be provided with concurrent access to concurrent debug signal activity of first and second data processing cores (core 2, core 1) embedded within the integrated circuit. A first signal path is provided from the first data processing core to a first pin (39) of the integrated circuit, for carrying a selected debug signal of the first data processing core to the first pin. A second signal path is provided from the second data processing core to the first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to the first pin. A third signal path is provided from the second data processing core to a second pin (41) of the integrated circuit for carrying the selected debug signal of the second data processing core to the second pin.

公开(公告)号：EP1605334A2

公开(公告)日：2005-12-14

申请号：EP05102655.7

申请日：2005-04-04

Applicant: TEXAS INSTRUMENTS DEUTSCHLAND GMBH

Inventor： Merk, Dieter

IPC: G06F1/22

CPC classification number: G01R31/31701 ,  G01R31/3172 ,  G06F1/22

Abstract: An interface circuit for a single logic input pin of an electronic system, comprising a decoder 10 for converting a pulse coded signal applied to said pin to a sequence of logic low and logic high values, and a state machine 12 responsive to said sequence of logic values to switch the electronic system between different modes of operation.

Abstract translation: 一种用于电子系统的单个逻辑输入引脚的接口电路，包括用于将施加到所述引脚的脉冲编码信号转换成逻辑低和逻辑高值的序列的解码器10以及响应所述逻辑序列的状态机12 在不同操作模式之间切换电子系统的值。

公开(公告)号：EP1488307A2

公开(公告)日：2004-12-22

申请号：EP03745656.3

申请日：2003-03-26

Applicant: Advanced Analogic Technologies, Inc.

Inventor： D'ANGELO, Kevin ,  BROWN, David, Alan ,  SUNG, John, K. ,  NILSSON, Jan ,  WILLIAMS, Richard, K.

IPC: G06F1/32

CPC classification number: G06F1/28 ,  G06F1/04 ,  G06F1/06 ,  G06F1/12 ,  G06F1/22 ,  G06F9/4403 ,  G06F13/4291 ,  G09G3/3406 ,  G09G5/10 ,  G09G2320/0233 ,  H05B33/0803 ,  H05B33/0815 ,  H05B33/0851

Abstract: A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.

公开(公告)号：EP1139108A3

公开(公告)日：2004-01-02

申请号：EP01200790.2

申请日：2001-03-02

Applicant: Texas Instruments Incorporated

Inventor： Swoboda, Gary L.

IPC: G01R31/3185

CPC classification number: G06F11/261 ,  G01R31/31705 ,  G01R31/318505 ,  G06F1/22 ,  G06F11/2733 ,  G06F11/3466

Abstract: A scan interface that includes control signals (TRST, TMS, TCK) and data signals (TDI, TDO) normally carried by respective signal paths of the scan interface can be used to carry signals other than signals of the scan interface. A first signal (TMS) and a second signal (TDO) can be time division multiplexed on the signal path that normally carries one of the signals, thereby freeing the signal path that carries the other of the signals to carry a signal other than a signal of the scan interface.

公开(公告)号：EP1139220A2

公开(公告)日：2001-10-04

申请号：EP01200792.8

申请日：2001-03-02

Applicant: Texas Instruments Incorporated

Inventor： Swoboda, Gary L. ,  McGowan, Robert A.

IPC: G06F11/26

CPC classification number: G06F11/261 ,  G01R31/31705 ,  G01R31/318505 ,  G06F1/22 ,  G06F11/2733 ,  G06F11/3466

Abstract: An emulation controller (12) located externally of an integrated circuit (14) can be provided with timing information indicative of operation of an internal clock of the integrated circuit that drives internal data processing activity of the integrated circuit. In response to each cycle of the internal clock, a corresponding digital bit is produced to represent the internal clock cycle, and the digital bits are output to the emulation controller at an output clock rate that differs from the clock rate of the internal clock.

Abstract translation: 位于集成电路（14）外部的仿真控制器（12）可以被提供有指示集成电路的内部时钟的操作的定时信息，其驱动集成电路的内部数据处理活动。 响应于内部时钟的每个周期，产生相应的数字位以表示内部时钟周期，并且以与内部时钟的时钟速率不同的输出时钟速率将数字位输出到仿真控制器。