摘要:
The present invention relates to a method and a mobile terminal for activating an InSIM chip. The mobile terminal comprises: a secure digital input/output SDIO port, configured to receive an InSIM chip activation command; a connection controller, configured to receive the InSIM chip activation command through the SDIO port, and establish a connection between the SDIO port and an InSIM chip according to the InSIM chip activation command; and the InSIM chip, configured to obtain activation information through the connection. In solutions of the present invention, an SDIO port of a mobile terminal is used to activate an InSIM chip, which does not require an extra InSIM chip test point on an exterior of the mobile terminal and is conducive to size reduction of the mobile terminal and electrostatic discharge protection.
摘要:
A stacking electronic system including a first master device, a second master device having a first connector, a second connector, and at least one slave device having a third connector is provided. The second and the third connectors have an error-proofing structure corresponding to each other, such that the first master device is structurally connected to the second master device to control the slave device directly.
摘要:
In one implementation, a cable harness switch includes a plurality of input ports, a first plurality of output ports, a second plurality of input ports, and a circuit switch module. Each input port from the plurality of input ports is configured to be coupled to a network link. Each output port from the first plurality of output ports is configured to be coupled to a network link. Each output port from the second plurality of output ports configured to be coupled to a network switch device. The circuit switch module is operatively coupled to the plurality of input ports, the first plurality of output ports, and the second plurality of output ports to define a network circuit including an input port from the plurality of input ports and an output port from the first plurality of output ports and the second plurality of output ports.
摘要:
A communication system has a monitor (31), memory (33,49) and one or more resources (35(i), 37(j), 39(k), 41(m), 43(n), 45(o), 47(p)). The memory (33,49) is connected to the monitor (31) and stores tasks and data. Each of the resources (35(i), 37(j), 39(k), 41(m), 43(n), 45(o), 47(p)) is connected to the monitor (31) and performs a function or executes a program. The bus (51) is implemented by a plurality of adjacent sections, each section being implemented as an ASIC connected to a resource.
摘要:
A data communication cable for connection between a mobile communication terminal and a computer includes: a USB connector connected to a USB port of the computer; a terminal connector connected to a UART port of the mobile communication terminal; a communication conversion chip in one of the USB connector and the terminal connector, the communication conversion chip converting signals for USB to UART; and a plurality of transmission cables connecting the USB connector and the terminal connector.
摘要:
Bei einer elektronischen Schaltung mit galvanisch getrennten Baugruppen erfolgt die Signalübertragung zwischen den Baugruppen A, B über eine Funkverbindung deren Reichweite einige Zentimeter beiträgt. Somit können Baugruppen A, B, die galvanisch getrennt sind, auch auf unterschiedlichen Leiterplatten LP1, LP2 angeordnet sein.
摘要:
A printed circuit board backpanel (100) uses strip-line construction to allow emitter coupled logic (ECL) signals and transistor-transistor logic (TTL) signals on the same signal layer, while providing electromagnetic interference (EMI) emission control. Disposed between ground layers (102,130), and separated bydielectric layers (104, 108, 112, 116, 120, 124, 128), are arranged signal layers (106, 114, 118, 126) and power layers (110, 122).
摘要:
A high speed data bus system for communication among various functional units (10). The functional units are mounted in immediately adjacent connectors (25) on the backplane (Fig. 4) to define a populated section of effective characteristic impedance Z0' and one or two unpopulated sections of impedance Z0. A populated end of the transmission line (40) is resistively terminated with a resistance corresponding to Z0' (65) while the unpopulated end is terminated with a resistance corresponding to Z0 (67). The border between the populated and unpopulated sections is terminated with a resistance corresponding to 1/(1Z0'-1/Z0) (68), thus eliminating signal reflections. Driver gating circuitry (Fig. 9B) responsive to first and second data input signals, an enable signal, and a conditional inversion input signal performs multiple levels of gating with minimum of propagation delay. The preferred differential receiver (Fig. 10B) amplifies a relatively low level differential input signal and performs an exclusive OR function with a conditional inversion signal. To implement the indivisibility of transfers the control logic for each port includes screening circuitry (190) responsive to the state of the port's buffers (180), and further responsive to flags from the functional unit for selectively accepting or rejecting bus information, and further includes screening constraint circuitry (230) ensure that the port accepts all or none of the information that makes up the transfer. Depending on the flag, the rejection may be total, or may apply only to a designated class of transfers.
摘要:
This application relates to a data access method and a computing device. The method is performed by a data processing unit connected to a processor. According to the method, after writing an access request into a first cache queue of the processor, the data processing unit sends, in a peripheral component interconnect express point-to-point transmission mode, a first instruction to a storage device to which an identifier of the storage device points, where the first instruction instructs the storage device to obtain the access request from the first cache queue and execute the access request. The access request includes the identifier of the storage device to be accessed, and the storage device is connected to the processor and not directly connected to the data processing unit. The first instruction includes location information of the access request in the first cache queue. Therefore, the data processing unit may directly access the host-side storage device, and does not need to access the storage device via the processor of a host, so that resources of the host are not occupied. In addition, this access manner can simplify a hardware connection manner and reduce hardware design complexity.