METHOD FOR ACTIVATING INSIM CHIP IN MOBILE TERMINAL AND MOBILE TERMINAL THEREFOR
    11.
    发明公开
    METHOD FOR ACTIVATING INSIM CHIP IN MOBILE TERMINAL AND MOBILE TERMINAL THEREFOR 审中-公开
    METHOD FOR A的InSIM芯片的移动终端中激活与移动端子

    公开(公告)号:EP2744249A1

    公开(公告)日:2014-06-18

    申请号:EP12871446.6

    申请日:2012-12-31

    发明人: GAO, Chunyu

    IPC分类号: H04W8/24

    CPC分类号: H04W8/22 G06F13/40 H04W8/265

    摘要: The present invention relates to a method and a mobile terminal for activating an InSIM chip. The mobile terminal comprises: a secure digital input/output SDIO port, configured to receive an InSIM chip activation command; a connection controller, configured to receive the InSIM chip activation command through the SDIO port, and establish a connection between the SDIO port and an InSIM chip according to the InSIM chip activation command; and the InSIM chip, configured to obtain activation information through the connection. In solutions of the present invention, an SDIO port of a mobile terminal is used to activate an InSIM chip, which does not require an extra InSIM chip test point on an exterior of the mobile terminal and is conducive to size reduction of the mobile terminal and electrostatic discharge protection.

    摘要翻译: 本发明涉及一种方法和用于在InSIM芯片激活的移动终端。 该移动终端包括:安全数字输入/输出端口SDIO,用于接收在InSIM芯片激活命令; 连接控制器,用于通过所述SDIO端口接收InSIM芯片激活命令,并建立SDIO端口之间和在InSIM芯片gemäß到InSIM芯片激活命令的连接; 和InSIM芯片,被配置为获得通过连接激活信息。 在本发明的移动终端的SDIO端口的解决方案,用于在InSIM芯片,这不会对向移动终端的外部需要额外InSIM芯片测试点的,有利于减小尺寸的移动终端的并激活 静电放电保护。

    Stacking electronic system
    12.
    发明公开
    Stacking electronic system 审中-公开
    Elektronisches Stapelungssystem

    公开(公告)号:EP2696293A1

    公开(公告)日:2014-02-12

    申请号:EP12195603.1

    申请日:2012-12-05

    申请人: Acer Incorporated

    发明人: Yeung, Sip Kim

    IPC分类号: G06F13/40 H05K7/14

    摘要: A stacking electronic system including a first master device, a second master device having a first connector, a second connector, and at least one slave device having a third connector is provided. The second and the third connectors have an error-proofing structure corresponding to each other, such that the first master device is structurally connected to the second master device to control the slave device directly.

    摘要翻译: 提供了包括第一主设备,具有第一连接器的第二主设备,第二连接器以及具有第三连接器的至少一个从设备的堆叠电子系统。 第二和第三连接器具有彼此对应的防错结构,使得第一主设备在结构上连接到第二主设备以直接控制从设备。

    CABLE HARNESS SWITCHES
    13.
    发明公开
    CABLE HARNESS SWITCHES 审中-公开
    开关线束

    公开(公告)号:EP2671365A1

    公开(公告)日:2013-12-11

    申请号:EP11857735.2

    申请日:2011-01-31

    IPC分类号: H04L29/10 H04L12/50

    CPC分类号: G06F13/40 H04L49/40 H04L49/60

    摘要: In one implementation, a cable harness switch includes a plurality of input ports, a first plurality of output ports, a second plurality of input ports, and a circuit switch module. Each input port from the plurality of input ports is configured to be coupled to a network link. Each output port from the first plurality of output ports is configured to be coupled to a network link. Each output port from the second plurality of output ports configured to be coupled to a network switch device. The circuit switch module is operatively coupled to the plurality of input ports, the first plurality of output ports, and the second plurality of output ports to define a network circuit including an input port from the plurality of input ports and an output port from the first plurality of output ports and the second plurality of output ports.

    MULTISECTIONAL BUS IN RADIO BASE STATION AND METHOD OF USING SUCH A RADIO BASE STATION
    14.
    发明公开
    MULTISECTIONAL BUS IN RADIO BASE STATION AND METHOD OF USING SUCH A RADIO BASE STATION 有权
    MULTISEKTIONSBUS在无线电基站和使用这些无线基站的方法

    公开(公告)号:EP1700225A1

    公开(公告)日:2006-09-13

    申请号:EP03786431.1

    申请日:2003-12-24

    发明人: HAGEMAN, Halbe

    IPC分类号: G06F13/40

    CPC分类号: G06F13/40

    摘要: A communication system has a monitor (31), memory (33,49) and one or more resources (35(i), 37(j), 39(k), 41(m), 43(n), 45(o), 47(p)). The memory (33,49) is connected to the monitor (31) and stores tasks and data. Each of the resources (35(i), 37(j), 39(k), 41(m), 43(n), 45(o), 47(p)) is connected to the monitor (31) and performs a function or executes a program. The bus (51) is implemented by a plurality of adjacent sections, each section being implemented as an ASIC connected to a resource.

    Data communication cable for connection between mobile communication terminal and computer
    15.
    发明公开
    Data communication cable for connection between mobile communication terminal and computer 审中-公开
    用于移动通信终端与计算机之间的连接的数据传输线缆

    公开(公告)号:EP1598743A3

    公开(公告)日:2006-09-13

    申请号:EP04015672.1

    申请日:2004-07-02

    申请人: Kang, Gil-Jong

    发明人: Kang, Gil-Jong

    IPC分类号: G06F13/40

    CPC分类号: G06F13/40

    摘要: A data communication cable for connection between a mobile communication terminal and a computer includes: a USB connector connected to a USB port of the computer; a terminal connector connected to a UART port of the mobile communication terminal; a communication conversion chip in one of the USB connector and the terminal connector, the communication conversion chip converting signals for USB to UART; and a plurality of transmission cables connecting the USB connector and the terminal connector.

    Galvanische Trennung mittels Funktechnologien

    公开(公告)号:EP1617337A2

    公开(公告)日:2006-01-18

    申请号:EP05012716.6

    申请日:2005-06-14

    IPC分类号: G06F13/40

    摘要: Bei einer elektronischen Schaltung mit galvanisch getrennten Baugruppen erfolgt die Signalübertragung zwischen den Baugruppen A, B über eine Funkverbindung deren Reichweite einige Zentimeter beiträgt. Somit können Baugruppen A, B, die galvanisch getrennt sind, auch auf unterschiedlichen Leiterplatten LP1, LP2 angeordnet sein.

    摘要翻译: 电子开关电路(S)具有两个构成块(A,B)。 它们可以安装在同一个电路板(LP)上,也可以安装在单独的电路板上。 每个构建块具有通过几条数据线连接到转换单元的微控制器。 转换单元具有连接到发射机 - 接收机单元(S / E1,S / E2)的发射和接收线路。 信号在两个构建块之间传输,无电接触。

    BUS SYSTEM.
    19.
    发明公开
    BUS SYSTEM. 失效
    总线系统。

    公开(公告)号:EP0091488A4

    公开(公告)日:1984-06-13

    申请号:EP82903545

    申请日:1982-10-19

    申请人: ELXSI

    摘要: A high speed data bus system for communication among various functional units (10). The functional units are mounted in immediately adjacent connectors (25) on the backplane (Fig. 4) to define a populated section of effective characteristic impedance Z0' and one or two unpopulated sections of impedance Z0. A populated end of the transmission line (40) is resistively terminated with a resistance corresponding to Z0' (65) while the unpopulated end is terminated with a resistance corresponding to Z0 (67). The border between the populated and unpopulated sections is terminated with a resistance corresponding to 1/(1Z0'-1/Z0) (68), thus eliminating signal reflections. Driver gating circuitry (Fig. 9B) responsive to first and second data input signals, an enable signal, and a conditional inversion input signal performs multiple levels of gating with minimum of propagation delay. The preferred differential receiver (Fig. 10B) amplifies a relatively low level differential input signal and performs an exclusive OR function with a conditional inversion signal. To implement the indivisibility of transfers the control logic for each port includes screening circuitry (190) responsive to the state of the port's buffers (180), and further responsive to flags from the functional unit for selectively accepting or rejecting bus information, and further includes screening constraint circuitry (230) ensure that the port accepts all or none of the information that makes up the transfer. Depending on the flag, the rejection may be total, or may apply only to a designated class of transfers.

    DATA ACCESS METHOD AND COMPUTING DEVICE
    20.
    发明公开

    公开(公告)号:EP4428684A1

    公开(公告)日:2024-09-11

    申请号:EP22899851.4

    申请日:2022-06-17

    发明人: QIN, Guo

    IPC分类号: G06F9/46

    摘要: This application relates to a data access method and a computing device. The method is performed by a data processing unit connected to a processor. According to the method, after writing an access request into a first cache queue of the processor, the data processing unit sends, in a peripheral component interconnect express point-to-point transmission mode, a first instruction to a storage device to which an identifier of the storage device points, where the first instruction instructs the storage device to obtain the access request from the first cache queue and execute the access request. The access request includes the identifier of the storage device to be accessed, and the storage device is connected to the processor and not directly connected to the data processing unit. The first instruction includes location information of the access request in the first cache queue. Therefore, the data processing unit may directly access the host-side storage device, and does not need to access the storage device via the processor of a host, so that resources of the host are not occupied. In addition, this access manner can simplify a hardware connection manner and reduce hardware design complexity.