公开(公告)号：EP2327282B1

公开(公告)日：2017-01-04

申请号：EP09807322.4

申请日：2009-08-13

Applicant: VIASYSTEMS TECHNOLOGIES CORP., L.L.C.

Inventor： KUMAR, Raj ,  DREYER, Monte ,  TAYLOR, Michael, J. ,  ZEPEDA, Ruben

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/46 ,  H05K3/42 ,  H05K3/40 ,  H05K3/38

CPC classification number: H05K3/4614 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/427 ,  H05K3/429 ,  H05K3/462 ,  H05K3/4623 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2203/0191 ,  H05K2203/0554 ,  H05K2203/061 ,  H05K2203/1152 ,  Y10T29/49128 ,  Y10T29/49156 ,  Y10T29/49165

公开(公告)号：EP1903840A4

公开(公告)日：2013-05-01

申请号：EP06767969

申请日：2006-07-07

Applicant: PANASONIC CORP

Inventor： HIGASHITANI HIDEKI

IPC: H05K1/11 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/4069 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/384 ,  H05K3/4614 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0373 ,  H05K2201/09827 ,  H05K2203/025 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/1461 ,  Y10T29/49124

公开(公告)号：EP2312923B1

公开(公告)日：2012-09-12

申请号：EP11001003.0

申请日：2006-07-07

Applicant: Ibiden Co., Ltd.

Inventor： Takahashi, Michimasa ,  Mikado, Yukinobu ,  Nakamura, Takenobu ,  Aoyama, Masakazu

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H01L23/48 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/00 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09709 ,  H05K2201/09827 ,  Y10T29/49124 ,  H01L2924/00

公开(公告)号：EP2421342A3

公开(公告)日：2012-08-15

申请号：EP11181849.8

申请日：2009-10-15

Applicant: FUJITSU LIMITED

Inventor： Mizukoshi, Masataka ,  Ishizuki, Yoshikatsu

IPC: H05K3/20 ,  H05K3/46 ,  H05K1/14

CPC classification number: H05K3/20 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1517 ,  H01L2924/15788 ,  H01L2924/1579 ,  H05K1/142 ,  H05K3/4658 ,  H05K3/4694 ,  H05K2201/0108 ,  H05K2201/0352 ,  H05K2201/09972 ,  H05K2203/025 ,  H05K2203/1189 ,  Y10T29/49117 ,  Y10T156/1052 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/16225

Abstract: [Problems] In an electronic component and a method of manufacturing the same, forming a finer conductive pattern than conventional counterpart.
[Means of Solving] A method of manufacturing an electronic component includes the steps of arranging a plurality of underlying substrates (131,132) each of which includes a recess portion (138a) formed on one major surface thereof; fitting a protrusion (140a) of a pattern formed on one major surface (140x) of a conductor plate (140) into the recess portion of each of the underlying substrates, and connecting the plurality of the underlying substrates through the conductor plate; forming a resin layer (139) on the one major surface of each of a plurality of the underlying substrates; and performing polishing, Chemical Mechanical Polishing, or cutting by the use of a diamond bit on another major surface of the conductor plate until the resin layer appears, and leaving the pattern in the resin layer as a conductor pattern.

公开(公告)号：EP2284882A4

公开(公告)日：2012-06-27

申请号：EP09758223

申请日：2009-05-22

Applicant: UNIV TOHOKU NAT UNIV CORP ,  FOUND ADVANCEMENT INT SCIENCE

Inventor： OHMI TADAHIRO ,  SUGAWA SHIGETOSHI ,  IMAI HIROSHI ,  TERAMOTO AKINOBU

IPC: H05K1/02 ,  H01L23/12 ,  H01L23/66 ,  H01P3/08 ,  H05K3/46

CPC classification number: H05K1/0218 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6688 ,  H01L2924/0002 ,  H01L2924/19032 ,  H01L2924/3011 ,  H05K1/025 ,  H05K1/0265 ,  H05K3/4652 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/0715 ,  H05K2201/096 ,  H05K2201/09618 ,  H05K2201/09727 ,  H05K2201/09972 ,  H01L2924/00

公开(公告)号：EP2421341A2

公开(公告)日：2012-02-22

申请号：EP11181847.2

申请日：2009-10-15

Applicant: FUJITSU LIMITED

Inventor： Mizukoshi, Masataka ,  Ishizuki, Yoshikatsu

IPC: H05K3/20 ,  H05K3/46

CPC classification number: H05K3/20 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/10175 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/83193 ,  H01L2224/838 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/1517 ,  H01L2924/15788 ,  H01L2924/1579 ,  H05K1/142 ,  H05K3/4658 ,  H05K3/4694 ,  H05K2201/0108 ,  H05K2201/0352 ,  H05K2201/09972 ,  H05K2203/025 ,  H05K2203/1189 ,  Y10T29/49117 ,  Y10T156/1052 ,  Y10T428/24917 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/01083 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2224/16225

Abstract: [Problems] In an electronic component and a method of manufacturing the same, forming a finer conductive pattern than conventional counterpart.
[Means of Solving] A method of manufacturing an electronic component includes the steps of connecting a pattern (100w) formed on one major surface (100x) of a conductor plate (100) to an electrode pad (98) of an underlying substrate (110); injecting a resin between the conductor plate and the underlying substrate, and forming a resin layer (103); and performing polishing, Chemical Mechanical Polishing, or cutting by the use of a diamond bit on another major surface of the conductor plate until the resin layer appears, and leaving the pattern in the resin layer as a conductor pattern.

Abstract translation: [问题]在电子部件及其制造方法中，形成比常规对应物更细的导电图案。 解决方法制造电子部件的方法包括以下步骤：将形成在导体板（100）的一个主表面（100x）上的图案（100w）连接到下面的基板（110）的电极焊盘（98） ）; 在导体板和下面的基板之间注入树脂，并形成树脂层（103）; 并进行抛光，化学机械抛光，或者通过在导体板的另一个主表面上使用金刚石钻头进行切割，直到出现树脂层，并将图案留在树脂层中作为导体图案。

公开(公告)号：EP1786035B1

公开(公告)日：2011-09-21

申请号：EP06023024.0

申请日：2006-11-06

Applicant: Semikron Elektronik GmbH & Co. KG Patentabteilung

Inventor： Göbl, Christian ,  Popp, Rainer

IPC: H01L25/16 ,  H05K1/14 ,  H05K7/20

CPC classification number: H01L25/165 ,  H01L23/3675 ,  H01L24/33 ,  H01L25/162 ,  H01L2924/1301 ,  H01L2924/13091 ,  H05K1/141 ,  H05K1/147 ,  H05K1/189 ,  H05K3/366 ,  H05K7/20445 ,  H05K7/209 ,  H05K2201/0352 ,  H05K2201/049 ,  H05K2201/09736 ,  H05K2201/10674 ,  Y10T428/24777 ,  Y10T428/31678 ,  H01L2924/00

公开(公告)号：EP1514459B1

公开(公告)日：2011-07-13

申请号：EP03727202.8

申请日：2003-04-11

Applicant: Curamik Electronics GmbH

Inventor： SCHULZ-HARDER, Jürgen ,  HABERL, Peter

IPC: H05K3/46

CPC classification number: H05K3/4667 ,  H01L23/3735 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/162 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/1301 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K1/0306 ,  H05K1/092 ,  H05K3/28 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/09972 ,  H05K2203/1476 ,  Y10T29/49227 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: The invention relates to a metal-ceramic substrate for electric circuits or modules, said substrate comprising a ceramic layer which is provided with at least one metallic layer of a first type applied to a surface of said ceramic layer in a plane manner. An insulating layer consisting of a glass-containing material is applied to at least one partial region of a surface of the metallic layer of the first type, said surface opposing the ceramic layer, and a metallic layer of a second type is applied to the insulating layer, the insulating layer and the metallic layer of a second type respectively being thinner then the ceramic layer and the metallic layer of the first type.

公开(公告)号：EP2312924A1

公开(公告)日：2011-04-20

申请号：EP11001004.8

申请日：2006-07-07

Applicant: Ibiden Co., Ltd.

Inventor： Takahashi, Michimasa ,  Mikado, Yukinobu ,  Nakamura, Takenobu ,  Aoyama, Masakazu

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H01L23/48 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/00 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09709 ,  H05K2201/09827 ,  Y10T29/49124 ,  H01L2924/00

Abstract: There is provided a multilayer printed wiring board in which each of insulating layers is 100 µm or less in thickness. Each of a plurality of viaholes electrically connecting conductor circuits on the insulating layers to each other is formed tapered inwardly from the surface of the insulating layer and the viaholes are disposed opposite to each other to form a multistage stacked via. This structure enables controlling such external stress as drop shock generated when the board is dropped and preventing the insulating substrate from warping, which leads to preventing cracking and disconnection of conductor circuit and minimizes the decrease of reliability and resistance to drop shock of the board.

公开(公告)号：EP2312923A1

公开(公告)日：2011-04-20

申请号：EP11001003.0

申请日：2006-07-07

Applicant: Ibiden Co., Ltd.

Inventor： Takahashi, Michimasa ,  Mikado, Yukinobu ,  Nakamura, Takenobu ,  Aoyama, Masakazu

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H01L23/48 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/00 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09709 ,  H05K2201/09827 ,  Y10T29/49124 ,  H01L2924/00

Abstract: There is provided a multilayer printed wiring board in which each of insulating layers is 100 µm or less in thickness. Each of a plurality of viaholes electrically connecting conductor circuits on the insulating layers to each other is formed tapered inwardly from the surface of the insulating layer and the viaholes are disposed opposite to each other to form a multistage stacked via. This structure enables controlling such external stress as drop shock generated when the board is dropped and preventing the insulating substrate from warping, which leads to preventing cracking and disconnection of conductor circuit and minimizes the decrease of reliability and resistance to drop shock of the board.