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    Improvements in analog to digital converters
    12.
    发明公开
    Improvements in analog to digital converters 失效
    模拟数字-Wandler。

    公开(公告)号：EP0098744A2

    公开(公告)日：1984-01-18

    申请号：EP83303814.4

    申请日：1983-06-30

    申请人： BELL & HOWELL LIMITED

    发明人： Wheable, Desmond ,  Attwood, Michael John

    IPC分类号： H03K13/02

    CPC分类号： H03M1/1205 ,  H03M1/38

    摘要： An analog to digital converter apparatus arranged to convert a plurality C (= 4) of different input signals to digital representations therof. The apparatus comprises a multiplexer arranged sequentially to couple each of the 4 input signals to a fast a-to-d converter (such as a successive approximations converter) at a rate such that each input signal is coupled N (= 8) times in a period M (= 20m secs) of an a.c. series mode interfacing signal (at 50 Hz) and at equal time intervals M/N (20/8 = 2.5m secs). The N (= 8) digital values of each input signal are averaged to provide at the end of a conversion period a digital value for each of the 4 input signals (C) which is the mean magnitude of the signal during the 20m sec period (M).

    摘要翻译： 一种模数转换器装置，被配置为将不同输入信号的多个C（= 4）转换为其数字表示。 该装置包括一个多路复用器，其按顺序设置，以使得每个输入信号在一个或多个输入信号中耦合N（= 8）倍的速率将4个输入信号中的每一个耦合到快速A / D变换器（例如逐次逼近转换器） 周期M（= 20 m secs）的交流 串联模式干扰信号（50 Hz）和等时间间隔M / N（20/8 = 2.5 m secs）。 每个输入信号的N（= 8）数字值被平均以在转换周期结束时提供四个输入信号（C）中的每一个的数字值，这是在20m秒周期期间信号的平均幅度 （M）。

    Analog to digital converter circuit
    13.
    发明公开
    Analog to digital converter circuit 失效
    模拟数字-Umsetzerschaltung。

    公开(公告)号：EP0096752A1

    公开(公告)日：1983-12-28

    申请号：EP83104641.2

    申请日：1980-03-06

    申请人： NEC CORPORATION

    发明人： Hareyama, Kyuichi

    IPC分类号： H03K5/24 ,  H03M1/38

    CPC分类号： H03K5/249 ,  H03K5/24 ,  H03M1/38

    摘要： An A/D converter comprising conversion means (51) for converting an analog voltage to an analog current, current means (54) for producing a plurality of weighted values of currents, combining means (56) for selectively combining the weighted values of currents, detection means (52, 55, 63, 68) for detecting difference in current value between the analog current and the combined current by the combining means (56), a differential amplifier (CMP) having a pair of inputs (SUM, BIAS), one (SUM) of which is supplied with a signal corresponding to the detected difference value, said detection means (52, 55, 63, 68) comprise first and second current mirror circuits (52, 55) input means (53, Q17, R10) responsive to said analog signal for applying an analog current having a value proportional to said analog signal to said input terminal of said first current mirror circuit (52), means (62) for connecting the output terminal of said first current mirror circuit (52) to the input terminal of said second current mirror circuit (55), and means for applying a reference signal to the output terminal of said second current mirror circuit (55). Preferably there are switch means (Q16) arranged between the pair or inputs (SUM, BIAS) of the differential amplifier (CMP), and control means (CK,59) for controlling the switch means (Q 16), wherein the switch means (Q16) is periodically made conductive to delete potential difference between the pair of inputs (SUM, BIAS) through the A/D conversion operation.

    摘要翻译： 一种A / D转换器，包括用于将模拟电压转换为模拟电流的转换装置（51），用于产生多个电流加权值的电流装置（54），用于选择性地组合电流的加权值的组合装置（56） 检测装置（52,55,63,68），用于通过组合装置（56）检测模拟电流和组合电流之间的电流值的差异;差分放大器（CMP），具有一对输入（SUM，BIAS）， 所述检测装置（52,55,63,68）包括第一和第二电流镜电路（52,55），输入装置（53，Q17，R10） ）响应于所述模拟信号，将具有与所述模拟信号成比例的值的模拟电流施加到所述第一电流镜电路（52）的所述输入端，用于将所述第一电流镜电路（52）的输出端 ）到所述输入端 第二电流镜电路（55），以及用于将参考信号施加到所述第二电流镜电路（55）的输出端的装置。 优选地，存在布置在差分放大器（CMP）的对或输入（SUM，BIAS）之间的开关装置（Q16）和用于控制开关装置（Q16）的控制装置（CK，59），其中开关装置 ）定期导通，以通过A / D转换操作删除一对输入（SUM，BIAS）之间的电位差。

    A transducer for sensing a variable parameter and for converting a so-obtained analog signal to a digital signal.
    15.
    发明公开
    A transducer for sensing a variable parameter and for converting a so-obtained analog signal to a digital signal. 失效
    Wandler zum Abtasten eines变量参数und zum Umwandeln eines so erhaltenen Analogsignals in ein digitales信号。

    公开(公告)号：EP0015253A4

    公开(公告)日：1980-05-21

    申请号：EP78900149

    申请日：1979-04-24

    申请人： ROSEMOUNT INC

    发明人： GRINDHEIM EARL A

    IPC分类号： G01L9/12 ,  G01R19/25 ,  G01R27/26 ,  H03M1/00 ,  H03M1/12 ,  H03K13/02 ,  G01M3/02 ,  H01G7/00

    CPC分类号： G01L9/12 ,  G01R27/2605 ,  H03M1/38

    摘要： A digital output capacitive transducer wherein two capacitors (C u, C u) are used, one (C u) providing a reference current and the other providing a varying signal current. The signal current is obtained from an oscillator (10) through a capacitor (C u), which varies in capacitance as a function of the parameter to be measured. The reference current offsets the signal current to attain a known relationship between the sampled parameter and the signal current. The circuit has a small number of components and operates on a relatively low voltage with an accurate digital output.

    摘要翻译： 使用两个电容器（Cu，Cu）的数字输出电容式换能器，一个（Cu）提供参考电流，另一个提供变化的信号电流。 信号电流通过电容器（Cu）从振荡器（10）获得，该电容器根据待测量的参数随电容而变化。 参考电流偏置信号电流以获得采样参数与信号电流之间的已知关系。 该电路具有少量的元件，并可在相对较低的电压下工作，并具有精确的数字输出。

    WIDE INPUT RANGE AND LOW NOISE COMPARATOR WITH TRIGGER TIMING CONTROL AND/OR GAIN BOOSTING
    16.
    发明公开
    WIDE INPUT RANGE AND LOW NOISE COMPARATOR WITH TRIGGER TIMING CONTROL AND/OR GAIN BOOSTING 审中-公开

    公开(公告)号：EP4358404A1

    公开(公告)日：2024-04-24

    申请号：EP23200668.4

    申请日：2023-09-28

    申请人： MediaTek Inc.

    发明人： HUANG, Wenchang

    IPC分类号： H03K5/24 ,  H03M1/38 ,  G06F13/16

    CPC分类号： H03K5/2481 ,  H03M1/38 ,  G06F13/1668

    摘要： A multi-stage comparator includes a first stage circuit, a second stage circuit, and a control circuit. The first stage circuit receives an input signal of the multi-stage comparator, generates a first-stage output signal according to the input signal, and outputs the first-stage output signal at an output port of the first stage circuit. The second stage circuit receives a second-stage input signal at an input port of the second stage circuit, and performs a second-stage operation to generate an output signal of the multi-stage comparator. The control circuit is coupled between the output port of the first stage circuit and the input port of the second stage circuit, and controls a start time of the second-stage operation.

    INPUT CIRCUIT FOR A DYNAMIC COMPARATOR
    18.
    发明公开
    INPUT CIRCUIT FOR A DYNAMIC COMPARATOR 审中-公开

    公开(公告)号：EP3331162A1

    公开(公告)日：2018-06-06

    申请号：EP16201696.8

    申请日：2016-12-01

    申请人： IMEC VZW

    发明人： MARTENS, Ewout ,  HERSHBERG, Benjamin ,  CRANINCKX, Jan

    IPC分类号： H03F3/45 ,  H03M1/36

    CPC分类号： H03M1/38 ,  H03F3/45179 ,  H03H19/004 ,  H03K5/2481 ,  H03M1/361

    摘要： The present invention relates to an Input circuit for a dynamic comparator comprising a positive and a negative branch, each branch comprising a transistor (T 1_n , T 1_p ) arranged for receiving an input voltage (V in,p , V in,n ) at its gate terminal and a first fixed voltage (V 1 ) at its drain terminal (D ip , D in ) via a first switch (SW 1n , SW 1p ) characterised in that the source terminal of said transistor in each of the positive and negative branch is connectable via a second switch (SW 2n , SW 2p ) to a first plate (S ip , S in ) of a first capacitor (C Sp ) in the positive branch and of a second capacitor (C Sn ) in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage (V 2p , V 2n ) and said input circuit further being arranged for receiving a first reset voltage (V hp ) on the first plate of the first capacitor in the positive branch and a second reset voltage (V hn ) on the first plate of the second capacitor in the negative branch, said first and second reset voltage being independent of each other.

    ASAR ADC CIRCUIT AND CONVERSION METHOD THEREOF
    19.
    发明公开
    ASAR ADC CIRCUIT AND CONVERSION METHOD THEREOF 审中-公开
    ASAR ADC电路及其转换方法

    公开(公告)号：EP3203636A1

    公开(公告)日：2017-08-09

    申请号：EP17152909.2

    申请日：2017-01-24

    申请人： Semiconductor Manufacturing International Corporation (Shanghai) ,  Semiconductor Manufacturing International Corporation (Beijing)

    发明人： Xun, Benpeng ,  Liu, Fei ,  Guo, Mengmeng ,  Tang, Hua ,  Yang, Haifeng

    IPC分类号： H03M1/12 ,  H03M1/46

    CPC分类号： H03M1/125 ,  H03M1/38 ,  H03M1/42 ,  H03M1/44 ,  H03M1/46

    摘要： The present invention provides asynchronous successive approximation register analog-to-digital converter (ASAR ADC) circuits and signal conversion method thereof. An exemplary ASAR AC circuit includes a sample/hold circuit configured to input a first analog signal and output a second analog signal; a digital-to-analog converter circuit configured to output a third analog signal; a first voltage comparison circuit configured to respond to a valid level of a latch signal, and output a first logic level and a second logic level; a first logic circuit configured to respond to a valid level of a flag signal, and identify a comparison result of the first voltage comparison circuit and output the first digit signal; and a pulse generation circuit configured to generate the latch signal and the flag signal with a generation time of the valid levels independently from the first logic level and the second logic level.

    摘要翻译： 本发明提供异步逐次逼近寄存器模数转换器（ASAR ADC）电路及其信号转换方法。 示例性ASAR AC电路包括：采样/保持电路，被配置为输入第一模拟信号并输出​​第二模拟信号; 数字 - 模拟转换器电路，被配置为输出第三模拟信号; 第一电压比较电路，被配置为响应于锁存信号的有效电平，并输出第一逻辑电平和第二逻辑电平; 第一逻辑电路，被配置为响应标志信号的有效电平，并识别第一电压比较电路的比较结果并输出第一数字信号; 以及脉冲生成电路，被配置为独立于所述第一逻辑电平和所述第二逻辑电平而生成具有有效电平的生成时间的所述锁存信号和所述标志信号。

    LC lattice delay line for high-speed ADC applications
    20.
    发明公开
    LC lattice delay line for high-speed ADC applications 审中-公开
    快速ADC应用LC-格延迟线

    公开(公告)号：EP2913929A3

    公开(公告)日：2016-03-02

    申请号：EP15156825.0

    申请日：2015-02-26

    申请人： Analog Devices Global

    发明人： Dong, Yunzhi ,  Li, Zhao ,  Schreier, Richard E. ,  Shibata, Hajime ,  Caldwell, Trevor Clifford

    IPC分类号： H03M1/14 ,  H03K5/159 ,  H03M1/06 ,  H03M3/00

    CPC分类号： H03K5/159 ,  H03M1/0626 ,  H03M1/14 ,  H03M1/145 ,  H03M1/38 ,  H03M3/414 ,  H03M3/464

    摘要： This disclosure describes techniques and methodologies of using passive continuous time (CT) delay line for high-speed CT analog-to-digital converter (ADC) applications. In a continuous-time residual producing stage common to these CT ADCs, a proper delay between the analog input and DAC output is crucial. Specifically, using an inductor-capacitor (LC) lattice based delay element to enable high-performance CT pipeline ADC and CT delta-sigma (ΔΣ) ADC. The use of an LC lattice based delay element provides wide-band group delay for continuous-time signals with well-controlled impedance. This will be an essential circuit component to build a high-performance CT ADCs especially in architectures where the generation of a low-noise and low-distortion residual between the CT signal and its digitized version is needed. LC lattice based delay element enables noise-free, distortion-free wideband delay that is required for high speed continuous-time pipeline ADC and delta-sigma ADC.