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    A method for producing an opto-electronic integrated circuit
    12.
    发明公开
    A method for producing an opto-electronic integrated circuit 失效
    Verfahren zum Herstellen einer integrierten optoelektronischen Schaltung。

    公开(公告)号：EP0331103A2

    公开(公告)日：1989-09-06

    申请号：EP89103486.0

    申请日：1989-02-28

    申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

    发明人： Sasaki, Goro c/o Yokohama Works of

    IPC分类号： H01L27/14 ,  H01L29/76 ,  H01L27/06

    CPC分类号： H01L27/1443 ,  Y10S148/119 ,  Y10S148/12

    摘要： Present invention is to provide a process for producing an opto-electronic integrated circuit comprising a field effect transistor as an electronic device and a photo-diode as an optical device both formed on an InP substrate,
    the field effect transistor comprising a high electron mobility transistor having:
    a GaInAs layer epitaxially grown on the InP substrate in a preset region thereof, a n-AlInAs layer epitaxially grown on the GaInAs layer, a gate electrode formed on the AlInAs layer, and a source electrode and a drain electrode formed on the AlInAs layer with the gate electrode therebetween, and
    the photo-diode comprising a PIN photo-diode having:
    the GaInAs layer epitaxially grown on the InP substrate near the region of the field effect transistor simultaneously with the growth of that of the field effect transistor, the n-AlInAs layer epitaxially grown on the GaInAs layer simultaneously with the growth of that of the field effect transistor, a n-InP layer epitaxially grown on the n-AlInAs layer, an undoped GaInAs layer epitaxially grown on the n-InP layer in a preset region thereof, a p-GaInAs layer epitaxially grown on the undoped GaInAs layer, an anode electrode formed on the p-GaInAs layer, and a cathode electrode formed on the n-InP layer near the undoped GaInAs layer.

    摘要翻译： 本发明提供一种制造光电集成电路的方法，所述光电集成电路包括作为电子器件的场效应晶体管和均匀地形成在InP衬底上的光电二极管，所述场效应晶体管包括高电子迁移率晶体管 具有：在其预置区域中在InP衬底上外延生长的GaInAs层，在GaInAs层上外延生长的n-AlInAs层，形成在AlInAs层上的栅电极和形成在AlInAs上的源电极和漏电极 层，其间具有栅电极，并且光电二极管包括PIN光电二极管，其具有在场效应晶体管的区域附近外延生长在InP衬底上的GaInAs层，同时场效应晶体管的生长， 在GaInAs层上外延生长的n-AlInAs层与场效应晶体管的生长同时生长，n-InP层外延生长在 n-AlInAs层，在其预置区域中在n-InP层上外延生长的未掺杂的GaInAs层，在未掺杂的GaInAs层外延生长的p-GaInAs层，形成在p-GaInAs层上的阳极电极和阴极 电极在未掺杂的GaInAs层附近形成在n-InP层上。

    Method of manufacturing semiconductor laser
    14.
    发明公开
    Method of manufacturing semiconductor laser 失效
    制造半导体激光的方法

    公开(公告)号：EP0420143A3

    公开(公告)日：1991-10-23

    申请号：EP90118380.6

    申请日：1990-09-25

    申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

    发明人： Kamei, Hidenori, c/o Yokohama Works

    IPC分类号： H01L33/00 ,  H01S3/19

    CPC分类号： H01S5/227 ,  H01L33/0062 ,  H01S5/2081 ,  H01S5/2201 ,  H01S5/2275 ,  Y10S148/026 ,  Y10S148/051 ,  Y10S148/095 ,  Y10S148/119 ,  Y10S148/169 ,  Y10S438/978

    摘要： According to this invention, a first cladding layer (2) of a first conductivity type, an active layer (3), a second cladding layer (4) of a second conductivity type, and a cap layer (5) much more susceptible to side etching than the second cladding layer (4) are sequentially grown on a (100) crystal plane of a semiconductor substrate (1) of the first conductivity type, and a stripe-like mask (7) extending in a direction is formed on the grown substrate to etch the stacked substrate. This etching is performed in a crystal orientation for forming an reverse triangular mesa. However, since the cap layer (5) is made of a material susceptible to side etching, a rounded mesa is formed. Thereafter, when a burying layer (10) is formed on the etched portion by a vapor phase epitaxy method, the burying layer (10) having a flat surface can be obtained depending on crystal orientations.

    Method of manufacturing semiconductor laser
    15.
    发明公开
    Method of manufacturing semiconductor laser 失效
    韦尔法罕zur Herstellung eines Halbleiterlasers。

    公开(公告)号：EP0420143A2

    公开(公告)日：1991-04-03

    申请号：EP90118380.6

    申请日：1990-09-25

    申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

    发明人： Kamei, Hidenori, c/o Yokohama Works

    IPC分类号： H01L33/00 ,  H01S3/19

    CPC分类号： H01S5/227 ,  H01L33/0062 ,  H01S5/2081 ,  H01S5/2201 ,  H01S5/2275 ,  Y10S148/026 ,  Y10S148/051 ,  Y10S148/095 ,  Y10S148/119 ,  Y10S148/169 ,  Y10S438/978

    摘要： According to this invention, a first cladding layer (2) of a first conductivity type, an active layer (3), a second cladding layer (4) of a second conductivity type, and a cap layer (5) much more susceptible to side etching than the second cladding layer (4) are sequentially grown on a (100) crystal plane of a semiconductor substrate (1) of the first conductivity type, and a stripe-like mask (7) extending in a direction is formed on the grown substrate to etch the stacked substrate. This etching is performed in a crystal orientation for forming an reverse triangular mesa. However, since the cap layer (5) is made of a material susceptible to side etching, a rounded mesa is formed. Thereafter, when a burying layer (10) is formed on the etched portion by a vapor phase epitaxy method, the burying layer (10) having a flat surface can be obtained depending on crystal orientations.

    摘要翻译： 根据本发明，第一导电类型的第一包层（2），有源层（3），第二导电类型的第二包层（4）和更容易受到侧面影响的覆盖层（5） 在第一导电型的半导体衬底（1）的（100）晶面上依次生长第二覆层（4）的蚀刻，并且形成沿<011>方向延伸的条状掩模（7） 在生长的衬底上以蚀刻堆叠的衬底。 该蚀刻以用于形成反向三角形台面的晶体取向进行。 然而，由于盖层（5）由易受侧面蚀刻的材料制成，因此形成圆形台面。 此后，当通过气相外延法在蚀刻部分上形成掩埋层（10）时，可以根据晶体取向获得具有平坦表面的掩埋层（10）。

    A method for producing an opto-electronic integrated circuit
    16.
    发明公开
    A method for producing an opto-electronic integrated circuit 失效
    一种用于生产光电集成电路的方法

    公开(公告)号：EP0331103A3

    公开(公告)日：1990-12-27

    申请号：EP89103486.0

    申请日：1989-02-28

    申请人： SUMITOMO ELECTRIC INDUSTRIES, LTD.

    发明人： Sasaki, Goro c/o Yokohama Works of

    IPC分类号： H01L27/14 ,  H01L29/76 ,  H01L27/06

    CPC分类号： H01L27/1443 ,  Y10S148/119 ,  Y10S148/12

    摘要： Present invention is to provide a process for producing an opto-electronic integrated circuit comprising a field effect transistor as an electronic device and a photo-diode as an optical device both formed on an InP substrate,
    the field effect transistor comprising a high electron mobility transistor having:
    a GaInAs layer epitaxially grown on the InP substrate in a preset region thereof, a n-AlInAs layer epitaxially grown on the GaInAs layer, a gate electrode formed on the AlInAs layer, and a source electrode and a drain electrode formed on the AlInAs layer with the gate electrode therebetween, and
    the photo-diode comprising a PIN photo-diode having:
    the GaInAs layer epitaxially grown on the InP substrate near the region of the field effect transistor simultaneously with the growth of that of the field effect transistor, the n-AlInAs layer epitaxially grown on the GaInAs layer simultaneously with the growth of that of the field effect transistor, a n-InP layer epitaxially grown on the n-AlInAs layer, an undoped GaInAs layer epitaxially grown on the n-InP layer in a preset region thereof, a p-GaInAs layer epitaxially grown on the undoped GaInAs layer, an anode electrode formed on the p-GaInAs layer, and a cathode electrode formed on the n-InP layer near the undoped GaInAs layer.

    Semiconductor processing
    18.
    发明公开
    Semiconductor processing 失效
    半导体的处理。

    公开(公告)号：EP0175436A2

    公开(公告)日：1986-03-26

    申请号：EP85303006.2

    申请日：1985-04-29

    申请人： NORTHERN TELECOM LIMITED

    发明人： Greene, Peter David ,  Renner, Daniel S.O. c/o Marijo Jones

    IPC分类号： H01L21/205 ,  H01L33/00 ,  C30B25/22

    CPC分类号： C23C16/4488 ,  H01L21/02392 ,  H01L21/02461 ,  H01L21/02543 ,  H01L21/02546 ,  H01S5/2095 ,  H01S5/227 ,  H01S5/2275 ,  Y10S148/065 ,  Y10S148/119

    摘要： A mass transport process for use in the manufacture of semiconductor devices, particularly but not exclusively low threshold semiconductor lasers in the InP/InGaAsP system, involves the arrangement of a cover wafer (18) of the material to be grown adjacent to a semiconductor wafer (15) on which the material is to be grown, their disposition together with a crystalline alkali halide (20) in a crucible (16), and heating the crucible, which is almost but not completely sealed, in a hydrogen stream.
    For the manufacture of InP/InGaAsP lasers and the growth of InP, the alkali halide may comprise KI, Rbl or Csl and a controlled amount of In metal (21) may be optionally contained in the crucible (16) to control the balance between growth of InP for defining the laser active region and erosion of InP from other areas of the wafer. Growth is achieved at temperatures comparable with liquid phase epitaxy processing temperatures.