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    MEMORY DEVICE
    11.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号：EP3518286A1

    公开(公告)日：2019-07-31

    申请号：EP17852595.2

    申请日：2017-03-23

    申请人： Toshiba Memory Corporation

    发明人： ITO, Mikihiko ,  KOYANAGI, Masaru ,  NAKATANI, Masafumi ,  OKUNO, Shinya ,  NAGASAKA, Shigeki ,  YOSHIHARA, Masahiro ,  UMEZAWA, Akira ,  TSUKIYAMA, Satoshi ,  KAWASAKI, Kazushige

    IPC分类号： H01L27/10

    摘要： A memory device according to one embodiment includes: a first memory chip including a first circuit, first and second terminals; a second memory chip including a second circuit and a third terminal; and an interface chip including first and a second voltage generation circuits. The second memory chip is provided above the first memory chip, and the interface chip is provided below the first memory chip. A first end of the first terminal is connected to the first circuit and a second end of the first terminal is connected to the first voltage generation circuit. A third end of the second terminal is connected to the third terminal and a fourth end of the second terminal is connected to the second voltage generation circuit. A fifth end of the third terminal is connected to the second circuit and a sixth end of the third terminal is connected to the second voltage generation circuit via the second terminal. In a direction perpendicular to a surface of the first memory chip, the third end overlaps with the sixth end, without overlapping with the fourth end.

    CURRENT SOURCE
    12.
    发明公开
    CURRENT SOURCE 审中-公开

    公开(公告)号：EP3514655A1

    公开(公告)日：2019-07-24

    申请号：EP17861693.4

    申请日：2017-10-03

    申请人： Asahi Kasei Microdevices Corporation

    发明人： SAKAMOTO Toshiro ,  TSUSHIMA Yuukou

    IPC分类号： G05F3/24 ,  G11C16/02 ,  G11C16/10 ,  H01L21/336 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    摘要： The object of the present invention is to provide a current source which is capable of suppressing an increase in circuit size and by which a highly accurate constant current extremely stable to manufacturing variations or temperature fluctuations can be obtained. A current source circuit (1) is provided with a nonvolatile storage element (M) having a control gate region (CG) and a source region (S) and operating as a field-effect transistor, and is configured to output a current in a state where a bias is applied between the control gate region (CG) and the source region (S).

    METHOD FOR PRODUCING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    18.
    发明公开
    METHOD FOR PRODUCING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 审中-公开
    制造半导体集成电路器件的方法和半导体集成电路器件

    公开(公告)号：EP3208831A1

    公开(公告)日：2017-08-23

    申请号：EP15850113.0

    申请日：2015-10-06

    申请人： Floadia Corporation

    发明人： TANIGUCHI Yasuhiro ,  KAWASHIMA Yasuhiko ,  KASAI Hideo ,  SAKURAI Ryotaro ,  SHINAGAWA Yutaka ,  OKUYAMA Kosuke

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L29/792 ,  H01L21/823456 ,  H01L27/088 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/42344

    摘要： A method for producing a semiconductor integrated circuit device, and a semiconductor integrated circuit device are disclosed. In the method, a first select gate electrode (G2a, G2b) and a second select gate electrode (G3a, G3b) electrically insulated from each other are formed in a memory circuit region (ER1) through a photomask process of forming a logic gate electrode (G5, G6) in a peripheral circuit region (ER2). Thus, even when the first select gate electrode (G2a or G2b) and the second select gate electrode (G3a, G3b) are formed to be separately controllable, an extra dedicated photomask process of fabricating only the memory circuit region (ER1) does not need to be performed in addition to a conventional dedicated photomask process of fabricating only a memory circuit region. Thereby, production cost is reduced accordingly.

    摘要翻译： 公开了一种制造半导体集成电路器件的方法和半导体集成电路器件。 在该方法中，通过形成逻辑栅电极的光掩模工艺在存储电路区域（ER1）中形成彼此电绝缘的第一选择栅电极（G2a，G2b）和第二选择栅电极（G3a，G3b） （G5，G6）在外围电路区域（ER2）中。 因此，即使当第一选择栅极电极（G2a或G2b）和第二选择栅极电极（G3a，G3b）形成为可单独控制时，仅制造存储器电路区域（ER1）的额外专用光掩模工艺也不需要 除了仅制造存储器电路区域的常规专用光掩模工艺之外，还要执行该工艺。 由此，生产成本相应降低。