利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

827 条记录 (耗时 0.021 秒)

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
    22.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME 审中-公开
    半导体元件及其制造方法

    公开(公告)号：EP2913854A4

    公开(公告)日：2016-07-20

    申请号：EP13848817

    申请日：2013-09-27

    申请人： FUJI ELECTRIC CO LTD

    发明人： ONOZAWA YUICHI

    IPC分类号： H01L21/329 ,  H01L21/336 ,  H01L29/06 ,  H01L29/167 ,  H01L29/36 ,  H01L29/40 ,  H01L29/739 ,  H01L29/861

    CPC分类号： H01L21/02351 ,  H01L21/02304 ,  H01L21/263 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/32 ,  H01L29/36 ,  H01L29/365 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66136 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/8611 ,  H01L29/868

    摘要： Proton implantation is performed a plurality of times to form a plurality of n-type buffer layers (5, 6, 7) in an n-type drift layer (2) at different depths from a rear surface of a substrate. The depth of the n-type buffer layer (5), which is provided at the deepest position from the rear surface of the substrate, from the rear surface of the substrate is more than 15 µm. The temperature of a heat treatment which is performed in order to change a proton into a donor and to recover a crystal defect after the proton implantation is equal to or higher than 400°C. In a carrier concentration distribution of the n-type buffer layer (5), a width from the peak position (5a) of carrier concentration to an anode is more than a width from the peak position (5a) to a cathode. The carrier concentration of regions (15, 16) interposed between the n-type buffer layers (5, 6, 7) is flat and is equal to or more than the carrier concentration of an n-type silicon substrate (1) and equal to or less than five times the carrier concentration of the n-type silicon substrate (1). Therefore, it is possible to ensure a breakdown voltage and to reduce generation loss. It is possible to suppress the oscillation of voltage and current during a switching operation. In addition, it is possible to recover the crystal defect and to reduce a leakage current. Accordingly, it is possible to reduce the risk of thermal runaway.

    RECESSED FIELD PLATE TRANSISTOR STRUCTURES
    23.
    发明公开
    RECESSED FIELD PLATE TRANSISTOR STRUCTURES 审中-公开
    采取场板的晶体管结构

    公开(公告)号：EP3008760A2

    公开(公告)日：2016-04-20

    申请号：EP14734340.4

    申请日：2014-06-02

    申请人： Cree, Inc.

    发明人： SRIRAM, Saptharishi ,  ALCORN, Terry ,  RADULESCU, Fabian ,  SHEPPARD, Scott

    IPC分类号： H01L29/778 ,  H01L29/40

    CPC分类号： H01L29/778 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7787

    摘要： A transistor device including a field plate is described. One embodiment of such a device includes a field plate separated from a semiconductor layer by a thin spacer layer. In one embodiment, the thickness of spacer layer separating the field plate from the semiconductor layers is less than the thickness of spacer layer separating the field plate from the gate. In another embodiment, the non-zero distance separating the field plate from the semiconductor layers is about 1500 Å or less. Devices according to the present invention can show capacitances which are less drain bias dependent, resulting in improved linearity.

    CASCODE STRUCTURES WITH GAN CAP LAYERS
    24.
    发明公开
    CASCODE STRUCTURES WITH GAN CAP LAYERS 审中-公开
    带有盖帽层的CASCODE结构

    公开(公告)号：EP3008759A1

    公开(公告)日：2016-04-20

    申请号：EP14733486.6

    申请日：2014-06-05

    申请人： Cree, Inc.

    发明人： SRIRAM, Saptharishi

    IPC分类号： H01L29/778 ,  H01L29/423 ,  H01L29/40

    CPC分类号： H01L29/778 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/7787

    摘要： A transistor device including a cap layer is described. One embodiment of such a device includes cap layer between a gate and a semiconductor layer. In one embodiment, the thickness of the cap layer is between 5 nm and 100 nm. In another embodiment, the cap layer can be doped, such as delta-doped or doped in a region remote from the semiconductor layer. Devices according to the present invention can show capacitances which are less drain bias dependent, resulting in improved linearity.

    摘要翻译： 描述包括盖层的晶体管器件。 这种器件的一个实施例包括在栅极和半导体层之间的覆盖层。 在一个实施例中，帽层的厚度在5nm和100nm之间。 在另一个实施例中，可以对帽层进行掺杂，诸如δ掺杂或掺杂在远离半导体层的区域中。 根据本发明的器件可以显示较小漏极偏置依赖性的电容，导致改善的线性。

    SEMICONDUCTOR DEVICE
    25.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开
    HALBLEITERBAUELEMENT

    公开(公告)号：EP2991119A3

    公开(公告)日：2016-04-13

    申请号：EP15181512.3

    申请日：2015-08-19

    申请人： Renesas Electronics Corporation

    发明人： KAWAGUCHI, Hiroshi

    IPC分类号： H01L29/778 ,  H01L29/792 ,  H01L21/336 ,  H01L29/423 ,  H01L29/41 ,  H01L29/20

    CPC分类号： H01L29/408 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/423 ,  H01L29/4234 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/66833 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/792

    摘要： The semiconductor device includes: a channel layer (CH), a barrier layer (BA), a first insulating film (IF1), and a second insulating film (IF2), each of which is formed above a substrate (S); a trench (T) that penetrates the second insulating film, the first insulating film, and the barrier layer to reach the middle of the channel layer; and a gate electrode (GE) arranged in the trench and over the second insulating film via a gate insulating film (GI). The bandgap of the second insulating film is smaller than that of the first insulating film, and the bandgap of the second insulating film is smaller than that of the gate insulating film. Accordingly, a charge (electron) can be accumulated in the second (upper) insulating film, thereby allowing the electric field strength at a corner of the trench to be improved. As a result, a channel is fully formed even at a corner of the trench, thereby allowing an ON-resistance to be reduced and an ON-current to be increased.

    摘要翻译： 半导体器件包括：形成在衬底（S）上方的沟道层（CH），势垒层（BA），第一绝缘膜（IF1）和第二绝缘膜（IF2））。 穿过第二绝缘膜，第一绝缘膜和阻挡层的沟槽（T）到达沟道层的中间; 以及通过栅极绝缘膜（GI）布置在沟槽中并在第二绝缘膜上方的栅电极（GE）。 第二绝缘膜的带隙小于第一绝缘膜的带隙，第二绝缘膜的带隙小于栅极绝缘膜的带隙。 因此，可以在第二（上）绝缘膜中积累电荷（电子），从而提高沟槽角部的电场强度。 结果，甚至在沟槽的拐角处完全形成沟道，从而允许导通电阻降低并且导通电流增加。

    SILICON CARBIDE SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD FOR SAME
    26.
    发明公开
    SILICON CARBIDE SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD FOR SAME 审中-公开
    碳化硅半导体器件及其制造方法

    公开(公告)号：EP2927939A1

    公开(公告)日：2015-10-07

    申请号：EP13859222.5

    申请日：2013-10-08

    申请人： Sumitomo Electric Industries, Ltd.

    发明人： HIYOSHI, Toru ,  SAITOH, Yu

    IPC分类号： H01L21/336 ,  H01L21/316 ,  H01L21/768 ,  H01L29/06 ,  H01L29/12 ,  H01L29/78

    CPC分类号： H01L29/42368 ,  H01L21/045 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/512 ,  H01L29/66068 ,  H01L29/7395 ,  H01L29/7811

    摘要： A silicon carbide substrate (10) includes a first impurity region (17), a well region (13) in contact with the first impurity region (17), and a second impurity region (14) separated from the first impurity region (17) by the well region (13). A first main surface (10a) includes a first region (10d) in contact with a channel region (CH), and a second region (10f) different from the first region (10d) A silicon-containing material (22a) is formed on the second region (10f) A first silicon dioxide region (15b) is formed on the first region (10d) A second silicon dioxide region (15c) is formed by oxidizing the silicon-containing material (22a). A gate runner (2) is electrically connected to a gate electrode (27) and formed in a position facing the second silicon dioxide region (15c) Consequently, a silicon carbide semiconductor device capable of achieving improved insulation performance between the gate runner and the substrate while the surface roughness of the substrate is suppressed, and a method of manufacturing the same can be provided.

    摘要翻译： 碳化硅衬底（10）包括第一杂质区（17），与第一杂质区（17）接触的阱区（13）以及与第一杂质区（17）分离的第二杂质区（14） 通过井区域（13）。 第一主表面（10a）包括与沟道区域（CH）接触的第一区域（10d）以及与第一区域（10d）不同的第二区域（10f）。含硅材料（22a）形成在第一主表面 第二区域（10f）在第一区域（10d）上形成第一二氧化硅区域（15b）。通过氧化含硅材料（22a）形成第二二氧化硅区域（15c）。 栅极流道（2）电连接到栅极电极（27）并且形成在面对第二二氧化硅区域（15c）的位置。因此，能够实现栅极流道和衬底之间的改善的绝缘性能的碳化硅半导体器件 同时抑制基板的表面粗糙度，并且可以提供制造该基板的方法。

    GaN based HEMTs with buried field plates
    28.
    发明授权
    GaN based HEMTs with buried field plates 有权
    GaN基HEMT的具有掩埋场板

    公开(公告)号：EP1921669B1

    公开(公告)日：2015-09-02

    申请号：EP07018026.0

    申请日：2007-09-13

    申请人： Cree, Inc.

    发明人： Yifeng, Wu

    IPC分类号： H01L21/335 ,  H01L29/423 ,  H01L29/778 ,  H01L29/40 ,  H01L29/812

    CPC分类号： H01L29/778 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/8128

    摘要： A transistor comprising an active region, with source and drain electrodes formed in contact with the active region and a gate formed between the source and drain electrodes and in contact with the active region. A first spacer layer is on at least part of the surface of the active region between the gate and the drain electrode and between the gate and the source electrode. The gate comprises a generally t-shaped top portion that extends toward the source and drain electrodes. A field plate is on the spacer layer and under the overhang of at least one section of the gate top portion. The field plate is at least partially covered by a second spacer layer, with the second spacer layer on at least part of the surface of the first active layer and between the gate and the drain and between the gate and the source. At least one conductive path electrically connects the field plate to the source electrode or the gate.