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31.发明公开Memory management for scalable compound instruction set machines with in-memory compounding 失效存储器管理用于使用存储器组合物可伸缩的可组装的命令集的计算机。
公开(公告)号：EP0463299A2
公开(公告)日：1992-01-02
申请号：EP91105247.0
申请日：1991-04-03
CPC分类号： G06F9/3808 , G06F9/30152 , G06F9/3802 , G06F9/3853
摘要： A digital computer system is described which is capable of processing two or more computer instructions in parallel and which has the capability of generating compounding tag information for those instructions, the compounding tag information being associated with instructions for the purpose of indicating groups of instructions which are to be concurrently executed. A compounding tag has a value which indicates the size of the group of instructions which are to be concurrently executed. The computer system includes a hierarchially-arranged memory which provides instructions to a CPU for execution. The instructions are compounded in the memory, and provision is made in the memory for storage of their compounding tags. In the event of modification of an instruction in memory, the invention provides for reduction of the value of the compounding tags for the modified instruction and instructions which are capable of being compounded with the modified instruction or for generation of new tag values for the modified instruction and instructions which are adjacent it in memory.
摘要翻译： 一种数字计算机系统被描述的所有其能够处理的两个并行或多个计算机指令的且具有产生用于那些指令复合标签信息的能力，该复合标签信息与指令相关联，用于指示是指示组的目的 同时被执行。 配混标签具有一个值，其指示该组的哪一个要被同时执行的指令的大小。 该计算机系统包括一个Hierarchially安排存储器，其提供指令以供执行的CPU。 该指令复合在内存中，并规定在内存做他们的复合标签的存储。 在存储器中的指令的修改的情况下，本发明提供了用于修正的指令和指令，其能够与修正的指令或用于产生新的标记值被复合为修正的指令减少的配合标记的值的 并说明它们为相邻它在内存中。
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32.发明公开Dynamic multiple instruction stream multiple data multiple pipeline floatingpoint unit 失效动态多指令流数字多数据管道浮动点单元
公开(公告)号：EP0328721A3
公开(公告)日：1990-07-18
申请号：EP88109842.0
申请日：1988-06-21
CPC分类号： G06F15/8092 , G06F9/30189 , G06F9/3851 , G06F9/3885 , G06F9/3889
摘要： A dynamic multiple instruction stream, multiple data, multiple pipeline (MIMD) apparatus simultaneously executes more than one instruction associated with a multiple number of instruction streams utilizing multiple data associated with the multiple number of instruction streams in a multiple number of pipeline processors. Since instructions associated with a multiple number of instruction streams are being executed simultaneously by a multiple number of pipeline processors, a tracking mechanism is needed for keeping track of the pipe in which each instruction is executing. As a result, a dynamic history table maintains a record of the pipeline processor number in which each incoming instruction is executing, and other characteristics of the instruction. When a particular instruction is received, it is decoded and its type is determined. Each pipeline processor handles a certain category of instructions; the particular instruction is transmitted to the pipeline processor having its corresponding category. However, before transmission, the pipeline processor is checked for completion of its oldest instruction by consulting the dynamic history table. If the table indicates that the oldest instruction in the pipeline processor should complete, execution of the oldest instruction in such processor completes, leaving room for insertion of the particular instruction therein for execution. When the particular instruction is transmitted to its associated pipeline processor, information including the pipe number is stored in the dynamic history table for future reference.
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33.发明公开High speed parity prediction for binary adders 失效HochgeschwindigkeitsparitätsvorausbestimmungfürbinäreAddierer。
公开(公告)号：EP0339296A2
公开(公告)日：1989-11-02
申请号：EP89105758.0
申请日：1989-04-01
IPC分类号： G06F11/10
摘要： Parity for every byte of the sum produced by addition of two operands is predicted based upon segmentation of each sum byte into three groups of adjacent bits, which leads to Boolean minterm circuitry employing a minimum of exclusive-OR gates.
摘要翻译： 通过添加两个操作数产生的和的每个字节的奇偶校验是基于将每个和字节分割成三组相邻位来预测的，这导致使用最小异或门的布尔最小电路。
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34.发明公开Apparatus for branch prediction for computer instructions 失效SprungvorhersagevorrichtungfürKomputerbefehle。
公开(公告)号：EP0328779A2
公开(公告)日：1989-08-23
申请号：EP88121547.9
申请日：1988-12-23
IPC分类号： G06F9/38
CPC分类号： G06F9/3844
摘要： An apparatus for branch prediction for computer instructions predicts the outcome of an executing branch instruction in response to instruction operands Q, R, and B. The apparatus includes combinatorial logic for predicting a first branch condition, ((Q+R)-B) > 0, or a second branch condition ((Q+R)-B) ≦ 0.
摘要翻译： 用于计算机指令的分支预测装置响应于指令操作数Q，R和B预测执行分支指令的结果。该装置包括用于预测第一分支条件的组合逻辑（（Q + R）-B） 0或第二分支条件（（Q + R）-B）
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35.发明公开Overlapped multiple-bit scanning multiplication system with banded partial product matrix 失效ÜberlappendesMehrbit untersuchendes Multipliziersystem mit einer Bandmatrix von Teilprodukten。
公开(公告)号：EP0314968A2
公开(公告)日：1989-05-10
申请号：EP88117226.6
申请日：1988-10-17
IPC分类号： G06F7/52
CPC分类号： G06F7/5336 , G06F7/49994
摘要： A multi-bit overlapped scanning multiplication system assembles modified partial products in a reduced, non-rectangular banded matrix. The rows of the matrix except for the first and last, are extended with bands of encoded extensions of limited length at the right and left ends of the partial product terms. The width of the significant bits of each partial product term is equal to q-1+S-2, where q is the width of the significant bits plus sign of the multiplicand and S is the number of bits which are overlapped scanned. Each partial product term is shifted S-1 bits from adjacent terms and is banded by encoded extensions to the terms. S-1 bits of encode are placed to the right of every terms except the last, the encode being based on the sign of the next partial product term; and S-1 bits of encoded sign extension are placed to the left of every term except the first, which has no sign extension, and last, to the left of which is placed an S bit encode. The bits of negative partial product terms are inverted, and a "hot 1" is encoded in the right extension in the previous row. The first bit of the multiplier is forced to zero so that the first partial product term is always positive or zero. Carry save adder trees are used to reduce each column of the matrix to two terms. When inputs to a carry save adder are known, the logic of the carry save adder is simplified to save chip space.
摘要翻译： 多比特重叠扫描乘法系统在经简化的非矩形带状矩阵中组装经修改的部分乘积。 除了第一和最后一行之外，矩阵的行在部分乘积项的右端和左端都以有限长度的编码扩展段扩展。 每个部分乘积项的有效位的宽度等于q-1 + S-2，其中q是有效位的宽度加被乘数的符号，S是重叠扫描的位数。 每个部分乘积项从相邻项移位S-1位，并通过条件的编码扩展进行带化。 编码的S-1位被放置在除了最后一个之外的每个术语的右侧，编码基于下一个部分乘积项的符号; 并且编码符号扩展的S-1位被放置在除了没有符号扩展的第一个之外的每个术语的左边，并且最后，其左侧被放置为S位编码。 负部分乘积项的位被反转，并且在上一行的右侧扩展中编码“热1”。 乘数的第一位被强制为零，使得第一个部分乘积项始终为正或零。 进位保存加法器树用于将矩阵的每列减少到两个项。 当输入到进位存储加法器是已知的，进位存储加法器的逻辑被简化以节省芯片空间。
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公开(公告)号：EP0509245B1
公开(公告)日：1999-05-19
申请号：EP92104378.2
申请日：1992-03-13
IPC分类号： G06F9/38
CPC分类号： G06F9/3853 , G06F9/383 , G06F9/3832 , G06F9/3844 , G06F9/3885
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38.发明公开Scalable massively parallel group partitioned diagonal-fold switching tree computing apparatus 失效可分级大型平行组合分离式对角切换树计算机
公开(公告)号：EP0569764A3
公开(公告)日：1994-07-13
申请号：EP93106731.8
申请日：1993-04-26
IPC分类号： G06F15/80
CPC分类号： G06N3/10 , G06F15/8023 , G06N3/063
摘要： A general massively parallel computer architecture supporting neural networks is developed utilizing a novel method of separating a triangular array containing N processing elements on each edge into multiple smaller triangular arrays, each of dimension X and each representing a common building block processor group chip, that can be interconnected for various size parallel processing implementations. The group chips are interconnected by a unique switching tree mechanism that maintains the complete connectivity capability and functionality possessed by the original triangular array of dimension N. A partitioning approach is presented first, where for a given size K and X, and K is divisible by X, it is proven that a triangular array containing K processor elements located on each edge of an equilateral triangular array can be partitioned into K/X triangular arrays of dimension X and K(K-X) / 2X ² square processor arrays of dimension X. An algorithm is presented next which partitions a square array into two triangular arrays, each of dimension X. Assuming K=N and the chosen technology supports the placement of a triangular processor group chip of dimension X on a single chip, the final scalable massively parallel computing structure for N root tree processors utilizes N ²/ X ² triangular processor group chips. Examples of using the partitioning methodology to create the scalable organization of processor elements are presented. Following these examples, an interconnection mechanism is developed which is shown to preserve the functionality of the original triangular array of dimension N in the implemented structure constructed of multiple triangular arrays of dimension X. Examples of the interconnection mechanism for two scaled neural network emulation massively parallel computers utilizing the same size X processor group chip are presented. Finally, an alternative scaling mechanism and implementation considerations for the interconnection mechanisms are discussed.
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公开(公告)号：EP0459222A3
公开(公告)日：1994-03-30
申请号：EP91107862.4
申请日：1991-05-15
IPC分类号： G06F15/80
摘要： The neural computing paradigm is characterized as a dynamic and highly parallel computationally intensive system typically consisting of input weight multiplications, product summation, neural state calculations, and complete connectivity among the neurons. Herein is described neural network architecture called SNAP which uses a unique intercommunication scheme within an array structure that provides high performance for completely connected network models such as the Hopfield model. SNAP's packaging and expansion capabilities are addressed, demonstrating SNAP's scalability to larger networks.
摘要翻译： 神经计算范例的特征是动态的和高度并行的计算密集系统，通常由输入权重乘法，乘积求和，神经状态计算以及神经元之间的完全连通性组成。 这里描述了称为SNAP的神经网络架构，其在阵列结构内使用独特的互通方案，为完全连接的网络模型（例如Hopfield模型）提供高性能。 SNAP的打包和扩展功能已得到解决，从而证明了SNAP对大型网络的可扩展性。
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40.发明公开A massively parallel diagonal fold tree array processor 失效Hochgradig平行机对角线轨道器Baumtabellenprozessor。
公开(公告)号：EP0569763A2
公开(公告)日：1993-11-18
申请号：EP93106730.0
申请日：1993-04-26
IPC分类号： G06F15/80
CPC分类号： G06F15/8023
摘要： A massively parallel processor apparatus having an instruction set architecture for each of the N ² the PEs of the structure. The apparatus which we prefer will have a PE structure consisting of PEs that contain instruction and data storage units, receive instructions and data, and execute instructions. The N ² structure should contain "N" communicating ALU trees, "N" programmable root tree processor units, and an arrangement for communicating both instructions, data, and the root tree processor outputs back to the input processing elements by means of the communicating ALU trees. The apparatus can be structured as a bit-serial or word parallel system. The preferred structure contains N ² PEs, identified a s PE column,row, in a N root tree processor system, placed in the form of a N by N processor array that has been folded along the diagonal and made up of diagonal cells and general cells. The Diagonal-Cells are comprised of a single processing element identified as PE i,i of the folded N by N processor array and the General-Cells are comprised of two PEs merged together, identified as PE i,j and PE j,i of the folded N by N processor array. Matrix processing algorithms are discussed followed by a presentation of the Diagonal-Fold Tree Array Processor architecture. The Massively Parallel Diagonal-Fold Tree Array Processor supports completely connected root tree processors through the use of the array of PEs that are interconnected by folded communication ALU trees.
摘要翻译： 具有用于该结构的每个N 2个PE的指令集架构的大规模并行处理器装置。 我们喜欢的设备将具有由PE组成的PE结构，该PE包含指令和数据存储单元，接收指令和数据以及执行指令。 N 2结构应包含“N”个通信ALU树，“N”个可编程根树处理器单元，以及用于将指令，数据和根树处理器输出传送回输入处理单元的装置，借助于 传播ALU树。 该装置可以被构造为比特串行或字并行系统。 优选的结构包含在N根树处理器系统中标识为PE列，行的N 2个PE，以N×N处理器阵列的形式放置，该处理器阵列已沿对角线折叠并由对角线单元组成 细胞。 对角线电池由单个处理元件组成，标识为折叠N个N处理器阵列的PEi，i，通用单元由合并在一起的两个PE组成，标识为折叠N的PEi，j和PEj，i 由N个处理器阵列。 讨论矩阵处理算法，然后介绍对角折叠树阵列处理器架构。 大型平行对角折叠树阵列处理器通过使用通过折叠通信ALU树互连的PE阵列来支持完全连接的根树处理器。
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